Abstract: Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.

Abstract: Technologies related to dynamic reconfiguration of programmable hardware are generally described. In some examples, coprocessor regions in programmable hardware such as a Field Programmable Gate Array (FPGA) may be dynamically assigned to transition the FPGA from a starting arrangement of coprocessor regions to an efficient arrangement. A placement algorithm may be executed to determine the efficient arrangement, and a path finding algorithm may be executed to determine path finding operations leading from the starting arrangement to the efficient arrangement. The path finding operations may be performed to implement the transition.

Abstract: Technologies related to secure system time reporting are generally described. In some examples, responses to some system time requests may be manipulated to prevent leaking information that may be of interest for timing attacks, while responses to other system time requests need not be manipulated. In particular, responses to system time requests that are separated from a previous system time request by a predetermined minimum value, or less, may be manipulated. Responses to system time requests that are separated from a previous system time request by more than the predetermined minimum value need not be manipulated. Furthermore, secure system time reporting may be adaptively deployed to servers in a data center on an as-needed basis.

Abstract: Various embodiments of a solar module design are disclosed. In some embodiments, a solar module comprises an optic having a sloped waveguide profile. The optic of the solar module is directly coupled to a receiver comprising a solar cell. The receiver is also coupled to a backplane of the module.

Abstract: An image processing method suitable for a printer unit, includes an error diffusion halftoning process arranged for quantizing and diffusing each pixel of an image including a set of subtractive primary colours (C?, M?, Y?), in an image including a quantized printer image including a set of ink drops (DC, DM, DY, Dc, Dm) of respective ink channels to be printed. The method comprises the step of determining, for each pixel, an input variable value (S) representing a measure of solvent quantity that should be ejected by the printer unit for each pixel, the input variable value being computed on the basis of the value of a corresponding pixel of the image including the set of subtractive primary colours (C?, M?, Y?), and of inputting the determined input variable value (S) in the error diffusion halftoning process together with the values of the corresponding pixel. The invention further relates to the apparatus embodying the method.

Abstract: An interferometer system includes a rhomboid assembly having a first optical stack and a second optical stack mounted on the first stack. The first stack includes a first prism having an angled face mounted to an angled face of a second prism. The interface between these angled faces includes a first polarizing beam-splitter. The second stack includes a third prism having an angled face mounted to an angled face of the fourth prism. The interface between these angled faces includes a second polarizing beam-splitter. First, second, third, and fourth wave plate elements are located in beam paths between the rhomboid assembly and at least one of a measurement optic and a reference optic. A redirecting optic is located at least adjacent to the vertical faces of the first and the third prisms.