Abstract: A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Abstract: A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated.

Abstract: A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated.

Abstract: A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing unit while the destination processing unit is processing program instructions, and accessing free-running, scan registers in clock-controlled components of the destination processing unit without interrupting processing of the program instructions by the destination processing unit. The access may be a read from status or mode registers of the destination processing unit, or write to control or mode registers. Many processing units can be interconnected in a ring topology, and the access command can be passed from the source processing unit through several other processing units before reaching the destination processing unit.

Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

Abstract: An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

Abstract: A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

Abstract: A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches.

Abstract: A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches.

Abstract: A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.