Patents by Inventor Kevin G. Chandler

Kevin G. Chandler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7170394
    Abstract: Disclosed is a novel technique for transferring power and signals between two electrical devices over a single wire pair. In particular, a remote sensor is connected to a host device. Power to the remote sensor is supplied through a voltage reference and control loop circuit that holds the voltage component of the power signal present on the wire pair constant during remote current sensing. The remote sensor itself can transmit measurements or information by driving a load on the sensor and thereby modulating the loop current. The current signal in the sensor-to-host loop can be a precision AC analog signal or a serial digital bit stream. Both types of signals can coexist using a multiplexing scheme.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: January 30, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Antonio Carlos Monte-Filho
  • Patent number: 6901336
    Abstract: A novel technique for transferring power, measurement signals, and communication signals between two electrical devices over a single wire pair is presented. A host device supplies power to a sensor device over the wire pair. The sensor device obtains A/C signals by modulating the current component of the power signal on the wire pair. The host device de-modulates the current component of the power signal on the wire pair to recover the A/C measurement signals. The sensor device generates a serial bit stream containing sensor communication signals, and modulates it with either the voltage-or current-component of the power signal present on the wire pair. The host device appropriately de-modulates the power signal to recover the serial bit stream containing the sensor communication signals.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: May 31, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Curtis Alan Tesdahl, David T. Crook, Kevin G. Chandler
  • Patent number: 6801863
    Abstract: A method and apparatus for detecting a resistive fault in an electrical conductor is presented. The apparatus of the invention includes an oscillating signal generator that applies an oscillating signal to the electrical conductor under test. The apparatus includes a measuring device for measuring the potential between the electrical conductor under test and a reference node. Such measurements are obtained both when the apparatus is disconnected from the electrical conductor under test and when the apparatus is connected to the electrical conductor under test. A difference in the measurements indicates that the connectivity of the electrical conductor is intact, whereas no difference indicates that a resistive fault exists somewhere in the electrical conductor. For greater accuracy, the longitudinal balance of the disconnected apparatus and connected apparatus measurements are calculated to determine connectivity.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: October 5, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Stephen Hird, John E Siefers, Kevin G Chandler
  • Publication number: 20040190464
    Abstract: Disclosed is a novel technique for transferring power, measurement signals, and communication signals between two electrical devices over a single wire pair. A host device supplies power to a sensor device over the wire pair. The sensor device obtains a/c measurement signals. The sensor device transmits the a/c measurement signals by modulating the current component of the power signal on the wire pair. The host device de-modulates the current component of the power signal on the wire pair to recover the a/c measurement signals. The sensor device generates a serial bit stream containing sensor communication signals, and modulates it with either the voltage- or current-component of the power signal present on the wire pair. The host device appropriately de-modulates the power signal to recover the serial bit stream containing the sensor communication signals. The host device may also generate a serial bit stream containing host communication signals.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Curtis Alan Tesdahl, David T. Crook, Kevin G. Chandler
  • Publication number: 20040181348
    Abstract: A method and apparatus for detecting a resistive fault in an electrical conductor is presented. The apparatus of the invention includes an oscillating signal generator that applies an oscillating signal to the electrical conductor under test. The apparatus includes a measuring device for measuring the potential between the electrical conductor under test and a reference node. Such measurements are obtained both when the apparatus is disconnected from the electrical conductor under test and when the apparatus is connected to the electrical conductor under test. A difference in the measurements indicates that the connectivity of the electrical conductor is intact, whereas no difference indicates that a resistive fault exists somewhere in the electrical conductor. For greater accuracy, the longitudinal balance of the disconnected apparatus and connected apparatus measurements are calculated to determine connectivity.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 16, 2004
    Inventors: Stephen Hird, John E. Siefers, Kevin G. Chandler
  • Patent number: 6291978
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, the driver of a first test channel applies a test signal to a selected node of the plurality of nodes. A predetermined amount of time after application of the test signal, the receiver of the first test channel reads a node voltage of the selected node. The node voltage is then compared to a predetermined threshold voltage of the receiver of the first test channel, and the result of the comparison is an indication as to whether the selected node is coupled to ground.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6191570
    Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: February 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6051979
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.
    Type: Grant
    Filed: July 25, 1999
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5977775
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node, at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: November 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5504432
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 2, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer