Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 sccm and 40 sccm for CHF3 and between about 10 sccm and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the device. In one embodiment, a heightened positive voltage and heightened negative voltage is applied to the semiconductor device while plasma etching is occurring to thereby induce charge to be removed from the semiconductor device.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate.

Abstract: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A method and apparatus for providing a positive voltage spike to a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Abstract: A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely within the chamber and includes ports for a gas conduit and a vacuum conduit. The container may be locked to the chamber through a locking mechanism and a recess in the container. The container may be guided into the chamber with a plurality of chamfers. The container may be used in inductively coupled plasma chambers, electron cyclotron resonance chambers, and chambers capable of receiving microwaves.

Abstract: A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the device. In one embodiment, a heightened positive voltage and heightened negative voltage is applied to the semiconductor device while plasma etching is occurring to thereby induce charge to be removed from the semiconductor device.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous-etchant.

Abstract: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: Plasma etching processes using a plasma containing fluorine as well as bromine and/or iodine are suited for high aspect ratio etching of trenches, contact holes or other apertures in silicon oxide materials. The plasma is produced using at least one fluorine-containing source gas and at least one bromine- or iodine-containing source gas. Bromine/iodine components of the plasma protect the aperture sidewalls from lateral attack by free fluorine, thus advantageously reducing a tendency for bowing of the sidewalls. Ion bombardment suppresses absorption of bromine/iodine components on the etch front, thus facilitating advancement of the etch front without significantly impacting taper.

Abstract: A plasma process reactor is disclosed that allows for greater control in varying the functional temperature range for enhancing semiconductor processing and reactor cleaning. The temperature is controlled by splitting the process gas flow from a single gas manifold that injects the process gas behind the gas distribution plate into two streams where the first stream goes behind the gas distribution plate and the second stream is injected directly into the chamber. By decreasing the fraction of flow that is injected behind the gas distribution plate, the temperature of the gas distribution plate can be increased. The increasing of the temperature of the gas distribution plate results in higher O2 plasma removal rates of deposited material from the gas distribution plate. Additionally, the higher plasma temperature aids other processes that only operate at elevated temperatures not possible in a fixed temperature reactor.

Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen under conditions effective to produce at least that portion of the one feature pattern in the feature layer to have a sidewall taper, if any, of less than or equal to 5° and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Other implementations are also contemplated.