Patents by Inventor Kevin Gomez
Kevin Gomez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11423927Abstract: A data storage system includes a data storage foil mounted within the data storage system, the data storage foil has at least one data storage surface. The data storage system also includes a head configured to interact with the at least one data storage surface to carry out at least one of data read or data write operations.Type: GrantFiled: June 21, 2021Date of Patent: August 23, 2022Assignee: Seagate Technology LLCInventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez, Brett R. Herdendorf, Dan Mohr
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Publication number: 20210312945Abstract: A data storage system includes a data storage foil mounted within the data storage system, the data storage foil has at least one data storage surface. The data storage system also includes a head configured to interact with the at least one data storage surface to carry out at least one of data read or data write operations.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez, Brett R. Herdendorf, Dan Mohr
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Patent number: 11043235Abstract: An apparatus includes a plurality of storage media mounted on a rotatable spindle. The apparatus also includes an actuator with at least one actuator arm configured to translate among the plurality of storage media and at least two heads supported on the at least one actuator arm. Each of the at least two heads is configured to communicate with the plurality of storage media.Type: GrantFiled: February 28, 2020Date of Patent: June 22, 2021Assignee: Seagate Technology LLCInventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez, Brett R. Herdendorf, Dan Mohr
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Patent number: 10811045Abstract: An apparatus includes a plurality of storage media mounted on a rotatable spindle. The apparatus also includes an actuator with at least one actuator arm configured to translate among the plurality of storage media and at least two heads supported on the at least one actuator arm. Each of the at least two heads is configured to communicate with the plurality of storage media.Type: GrantFiled: April 27, 2018Date of Patent: October 20, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez
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Publication number: 20200202891Abstract: An apparatus includes a plurality of storage media mounted on a rotatable spindle. The apparatus also includes an actuator with at least one actuator arm configured to translate among the plurality of storage media and at least two heads supported on the at least one actuator arm. Each of the at least two heads is configured to communicate with the plurality of storage media.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez, Brett R. Herdendorf, Dan Mohr
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Patent number: 10521287Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.Type: GrantFiled: October 5, 2018Date of Patent: December 31, 2019Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
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Publication number: 20190333533Abstract: An apparatus includes a plurality of storage media mounted on a rotatable spindle. The apparatus also includes an actuator with at least one actuator arm configured to translate among the plurality of storage media and at least two heads supported on the at least one actuator arm. Each of the at least two heads is configured to communicate with the plurality of storage media.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Riyan Alex Mendonsa, Edward Charles Gage, Kevin Gomez
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Patent number: 10452281Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.Type: GrantFiled: November 9, 2015Date of Patent: October 22, 2019Assignee: SEAGATE TECHNOLOGY LLCInventors: Jonathan W Haines, Timothy R Feldman, Wayne H Vinson, Ryan J Goss, Kevin Gomez, Mark Allen Gaertner
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Publication number: 20190042343Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.Type: ApplicationFiled: October 5, 2018Publication date: February 7, 2019Inventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
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Patent number: 10095568Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.Type: GrantFiled: April 27, 2017Date of Patent: October 9, 2018Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
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Publication number: 20180225164Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.Type: ApplicationFiled: April 27, 2017Publication date: August 9, 2018Inventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
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Patent number: 9727459Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.Type: GrantFiled: August 22, 2014Date of Patent: August 8, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Antoine Khoueir, Ryan James Goss, Jon Trantham, Kevin Gomez, Frank Dropps
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Patent number: 9489148Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.Type: GrantFiled: March 13, 2013Date of Patent: November 8, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Ryan James Goss, Jon D. Trantham, Antoine Khoueir, David Scott Ebsen, Mark Allen Gaertner, Kevin Gomez
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Publication number: 20160188226Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.Type: ApplicationFiled: November 9, 2015Publication date: June 30, 2016Applicant: SEAGATE TECHNOLOGY LLCInventors: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson, Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Publication number: 20160054940Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.Type: ApplicationFiled: August 22, 2014Publication date: February 25, 2016Inventors: Antoine Khoueir, Ryan James Goss, Jon Trantham, Kevin Gomez, Frank Dropps
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Patent number: 9183134Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.Type: GrantFiled: April 22, 2010Date of Patent: November 10, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson, Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Patent number: 8949567Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.Type: GrantFiled: February 26, 2013Date of Patent: February 3, 2015Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Jon D. Trantham, Kevin Gomez, Ara Patapoutian
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Publication number: 20140281280Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Ryan James Goss, Jon D. Trantham, Antoine Khoueir, David Scott Ebsen, Mark Allen Gaertner, Kevin Gomez
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Publication number: 20140244946Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: Seagate Technology LLCInventors: Antoine Khoueir, Jon D. Trantham, Kevin Gomez, Ara Patapoutian
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Patent number: 8799747Abstract: Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations.Type: GrantFiled: June 3, 2010Date of Patent: August 5, 2014Assignee: Seagate Technology LLCInventors: Ryan James Goss, David Seekins, Mark Allen Gaertner, Kevin Gomez