Abstract: Methods for screening of affinity reagents for many target proteins of interest simultaneously. Arrayed targets (e.g., peptide, protein, RNA, cell, etc.) are used in affinity selection experiments to reduce the amount of target needed and to improve the throughput of discovering recombinant affinity reagents to a large collection of targets.

Abstract: Provided herein are compositions and methods for identifying cancer cells. In particular, provided herein are optimized assays for identifying a variety of different cancer cells present in a sample at low concentrations.

Abstract: Methods for screening of affinity reagents for many target proteins of interest simultaneously. Arrayed targets (e.g., peptide, protein, RNA, cell, etc.) are used in affinity selection experiments to reduce the amount of target needed and to improve the throughput of discovering recombinant affinity reagents to a large collection of targets.

Abstract: Methods for screening of affinity reagents for many target proteins of interest simultaneously. Arrayed targets (e.g., peptide, protein, RNA, cell, etc.) are used in affinity selection experiments to reduce the amount of target needed and to improve the throughput of discovering recombinant affinity reagents to a large collection of targets.

Abstract: Provided herein are antibodies and related molecules that bind to N-cadherin. In particular, provided herein are antibodies and related molecules that binding to canine N-cadherin and uses thereof (e.g., for identifying a variety of different cancer cells).

Abstract: Provided herein are compositions and methods for identifying cancer cells. In particular, provided herein are assays for identifying copy number variations (e.g., in circulating tumor cells (CTC)) indicative of cancer (e.g., lymphoma).

Abstract: Provided herein are compositions and methods for identifying cancer cells. In particular, provided herein are optimized assays for identifying a variety of different cancer cells present in a sample at low concentrations.

Abstract: Methods for screening of affinity reagents for many target proteins of interest simultaneously. Arrayed targets (e.g., peptide, protein, RNA, cell, etc.) are used in affinity selection experiments to reduce the amount of target needed and to improve the throughput of discovering recombinant affinity reagents to a large collection of targets.

Abstract: A window assembly (30) comprising a frame (36) in which are received sliding and security members. The security member has ventilating and non-ventilating parts (40, 32), with the sliding member (34) being slidably moveable over the security member between a first position in which air may pass through the ventilating part (40) so as to ventilate the room in which the window assembly (30) is located, and a second position in which no such ventilation can occur. The ventilating part 40 may comprise a grille, perforated sheet, lattice arrangement or the like.

Abstract: A window assembly (30) comprising a frame (36) in which are received sliding and security members. The security member has ventilating and non-ventilating parts (40, 32), with the sliding member (34) being slidably moveable over the security member between a first position in which air may pass through the ventilating part (40) so as to ventilate the room in which the window assembly (30) is located, and a second position in which no such ventilation can occur. The ventilating part 40 may comprise a grille, perforated sheet, lattice arrangement or the like.

Abstract: A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded.

Abstract: In some implementations, methods and apparatus, including computer program products, facilitate microtransactions over electronic networks by providing an electronic points currency that can be purchased in bulk and used for purchasing goods and services in microtransactions. In a typical implementation, points may be purchased in bulk quantities that have a value that is large relative to the price of a single product that may be purchased in a microtransaction. A microtransaction vendor may offer products for sale at a discount by setting a first price for purchases made with a credit card and a second lower price for purchases made using points.

Abstract: A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester, comprising: a built-in self test (BIST) engine coupled to the integrated circuit; a clock multiplier adapted to derive a high speed clock signal from a clock signal supplied by the low speed tester, wherein the high speed clock signal drives the testing of the high speed integrated circuit; and an edge shaper coupled to the clock multiplier and the BIST engine, the edge shaper configured to output a plurality of different shaped clock signals.

Abstract: A method and apparatus for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with a redundant element.

Abstract: A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).

Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

Abstract: Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract: An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in real-time. Architecture (20) includes a first memory element (22) (FME 22) having a register (24), a second memory element (26) (SME 26) having a register (28), a third memory element (30) (TME 30) having a register (32), and a finite state machine (34) (FSM 34) having a decision algorithm (36). FME (22), SME (26), TME (30), and FSM (34) are electrically connected to a built-in self-test (BIST) module (38). BIST module (38) outputs failed row and column addresses (40), also referred to as “fails,” for rows and columns that are identified as defective during the BIST to the memory elements and FSM (34). FSM (34) allocates redundancy resources of the memory system according to decision algorithm (36).

Abstract: A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.

Abstract: A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.