Patents by Inventor Kevin Guan
Kevin Guan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140218350Abstract: In general, in one aspect, a display controller has non-essential portions powered off for a portion of vertical blanking interval (VBI) periods to conserve power. The portion takes into account overhead for housekeeping functions and memory latency for receiving a first packet of pixels for a frame to be decoded during a next active period. Gating circuitry may gate power to the non-essential portions starting at beginning of the VBI periods. A latency predictor may predict the portion of the VBI periods by predicting the memory latency for a next VBI period and subtracting the predicted memory latency from the VBI period. The memory latency for the next VBI period may be predicted by adding an average difference between successive actual memory latencies for a plurality of VBI periods to an actual memory latency for previous VBI period. A constant delay may also be subtracted from the VBI period.Type: ApplicationFiled: December 13, 2012Publication date: August 7, 2014Inventors: Kevin Guan Ming Wee, Chin Seng Lu, Pei Jin Lim, Lee Teck Henry Lim
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Patent number: 8680686Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.Type: GrantFiled: June 29, 2010Date of Patent: March 25, 2014Assignee: Spansion LLCInventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Thor Lee Lee, Sally Foong, Kevin Guan
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Patent number: 8357563Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.Type: GrantFiled: August 10, 2010Date of Patent: January 22, 2013Assignee: Spansion LLCInventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Koo Eng Luon, Sally Foong, Kevin Guan
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Publication number: 20120038059Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Koo Eng LUON, Sally FOONG, Kevin GUAN
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Publication number: 20110316158Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Thor Lee LEE, Sally FOONG, Kevin GUAN
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Patent number: 7932131Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.Type: GrantFiled: November 5, 2007Date of Patent: April 26, 2011Assignee: Spansion LLCInventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho
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Patent number: 7750481Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: GrantFiled: December 9, 2008Date of Patent: July 6, 2010Assignee: Spansion LLCInventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong
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Patent number: 7674653Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: GrantFiled: December 9, 2008Date of Patent: March 9, 2010Assignee: Spansion LLCInventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong
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Patent number: 7554204Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: GrantFiled: June 18, 2007Date of Patent: June 30, 2009Assignee: Spansion LLCInventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong
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Publication number: 20090115033Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.Type: ApplicationFiled: November 5, 2007Publication date: May 7, 2009Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho
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Publication number: 20090091043Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Inventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong
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Publication number: 20090093084Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Inventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong
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Publication number: 20080308947Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.Type: ApplicationFiled: June 18, 2007Publication date: December 18, 2008Inventors: Nguk Chin Lai, Kevin Guan, Kwet Nam Wong, Cheng Sim Kee, Sally Foong