Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for programmatically generating a graphical program in response to state diagram information. The state diagram information may specify a plurality of states and state transitions, wherein each state transition specifies a transition from a first state to a second state. A graphical program generation program (GPG program), may receive the state diagram information and automatically, i.e., programmatically, generate a graphical program (or graphical program portion) based on the state diagram information. The GPG program may programmatically include graphical source code in a block diagram of the graphical program, which may serve as a framework of the states specified by the state diagram information and the state transitions among the states.

Abstract: A system and method for programmatically generating a graphical program in response to state diagram information. The state diagram information may specify a plurality of states and state transitions, wherein each state transition specifies a transition from a first state to a second state. A graphical program generation program (GPG program), may receive the state diagram information and automatically, i.e., programmatically, generate a graphical program (or graphical program portion) based on the state diagram information. The GPG program may programmatically include graphical source code in a block diagram of the graphical program, which may serve as a framework of the states specified by the state diagram information and the state transitions among the states.

Abstract: System and method for creating a graphical program that uses multiple models of computation (MoC). A first plurality of graphical program elements is assembled in a graphical program in response to first input, where the assembled first plurality of graphical program elements have a first MoC. A structure is displayed in the graphical program indicating use of a second MoC for graphical program elements comprised within the interior of the structure. A second plurality of graphical program elements is assembled within the structure in response to second input, where the assembled second plurality of graphical program elements have the second MoC. The graphical program is executable to perform a function, for example, by executing the assembled first plurality of graphical program elements in accordance with the first model of computation, and executing the assembled second plurality of graphical program elements in accordance with the second model of computation.

Abstract: One embodiment of the present invention relates to disabling graphical code in a graphical program. A first portion of the graphical program may be disabled, which may include preventing the first portion of the graphical program from being compiled and/or preventing the first portion of the graphical program from being executed. Another embodiment of the invention relates to conditionally compiling graphical code in a graphical program. A first portion of the graphical program may be compiled if one or more associated conditions are true, or may not be compiled otherwise.

Abstract: System and method for creating and executing a graphical program. A first plurality of graphical program elements (GPEs) having a first model of computation (MoC), e.g., homogenous dataflow, are assembled in a graphical program in response to first input. A structure, including an interior portion, is displayed in the graphical program, indicating use of a second MoC, e.g., multi-rate dataflow, for GPEs within the interior portion. A second plurality of GPEs having the second MoC are assembled within the interior portion of the structure in response to second input. The second plurality of GPEs are converted into a new third plurality of GPEs having the first MoC, e.g., by parsing the second plurality of GPEs to determine multiple primitives according to the second MoC, determining the third plurality of GPEs based on the primitives, and assembling the third plurality of GPEs in the graphical program.

Abstract: System and method for creating a graphical program that uses multiple models of computation (MoC). A first plurality of graphical program elements is assembled in a graphical program in response to first input, where the assembled first plurality of graphical program elements have a first MoC. A structure is displayed in the graphical program indicating use of a second MoC for graphical program elements comprised within the interior of the structure. A second plurality of graphical program elements is assembled within the structure in response to second input, where the assembled second plurality of graphical program elements have the second MoC. The graphical program is executable to perform a function, for example, by executing the assembled first plurality of graphical program elements in accordance with the first model of computation, and executing the assembled second plurality of graphical program elements in accordance with the second model of computation.

Abstract: System and method for generating a data flow diagram. A first case structure may be specified. Each case of the first case structure that includes a respective plurality of input bound data flow nodes may be partitioned into one or more data flow diagram portions. The first case structure may be replaced with a first conditional structure and one or more second conditional structures. The first conditional structure may be operable to select one or more of the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The one or more second conditional structures may be operable to select at least one output from the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The partitioning and replacing may be performed automatically in response to specification of the first case.

Abstract: System and method for generating a data flow diagram. A data flow diagram is provided that includes one or more non-input bound data flow (NIBDF) nodes, each with a respective functionality, and at least one of which is a subsystem node representing a non-input bound data flow sub-diagram comprising a plurality of interconnected nodes. All non-input bound data flow nodes in the data flow diagram are converted into input bound data flow (IBDF) nodes to produce an IBDF diagram, including: for each NIBDF subsystem node in the data flow diagram: partitioning the NIBDF sub-diagram into a plurality of IBDF sub-diagrams that operate according to input bound data flow semantics without changing data dependencies of the NIBDF sub-diagram, and including a plurality of IBDF nodes respectively representing the plurality of IBDF sub-diagrams in the IBDF diagram in lieu of the NIBDF subsystem node. The IBDF diagram is then stored.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram.

Abstract: A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Abstract: System and method for programmatically generating a graphical program in response to state diagram information. The state diagram information specifies a plurality of states and state transitions. A graphical program generation program (GPG program), receives the state diagram information and automatically, i.e., programmatically, generates a graphical program (or graphical program portion) based on the state diagram information. The GPG program automatically includes graphical source code in a block diagram of the graphical program, which serves as a framework of the states specified by the state diagram information and the state transitions, with various “placeholders” or “containers” enabling the user to easily fill in the graphical program with source code specifying execution instructions for each state and Boolean conditions for each state transition.

Abstract: Methods and apparatus, including computer program products, implementing a technique for repairing links in a file. The file can contain one or more links, each link referring to a target file. For one or more of the links, a file identifier such as a file name, file number, or file address is stored. Alternatively, for one or more of the links, target information is stored that identifies an old target and a new target for the link. The links can be repaired based on the stored information. The stored information can be used to identify changes to the links that occurred while the file containing the link was inaccessible to the system, for example, due to the file being locked by a user.

Abstract: Methods and apparatus, including computer program products, implementing a technique for repairing links in a file. The file can contain one or more links, each link referring to a target file. For one or more of the links, a file identifier such as a file name, file number, or file address is stored. Alternatively, for one or more of the links, target information is stored that identifies an old target and a new target for the link. The links can be repaired based on the stored information. The stored information can be used to identify changes to the links that occurred while the file containing the link was inaccessible to the system, for example, due to the file being locked by a user.