Abstract: A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.

Abstract: A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.

Abstract: A method for manufacturing a chip size package comprises the steps of: providing a chip having a plurality of bonding pads on its active surface; providing a metal board consisting of the upper layer and the lower layer, wherein, a chip carrier, corresponding to said least chip, being formed on the surface of the upper layer of the said metal board; selectively etching the upper layer of the metal board to form a plurality of redistribution conductive circuits supported by the lower layer of the metal board; securing the chip to the chip carrier of the upper layer of the metal board, and electrically connecting to the conductive circuits; providing a package body (or underfill) in between the chip and the upper layer of the metal board; and, removing the lower layer of the metal board. Thus, package manufactured by applying present invention has ability of securing more electrodes and thinner thickness.