Abstract: A method and apparatus for controlling connectivity comprising a connectivity control element coupled between an interface connector and an interface circuit, and an interface controller, coupled to the connectivity control element, for authenticating a peripheral device and controlling connectivity between the interface connector and the interface circuit based upon authentication of the peripheral device.

Abstract: A method and apparatus for building a packet grooming and aggregation engine is disclosed. The grooming and aggregation engine can be applied to the network for providing flexible aggregation and service multiplexing functions. A method and apparatus achieves the intended function that is easy to implement and easy for the network operator to manage, yet provides enough flexibility to mix and match various services at the edge node of the network. One specific embodiment of the patent is an Ethernet over SONET mapping system where user traffic is aggregated and groomed into SONET transport virtual concatenation channels.

Abstract: A method of reducing error-multiplication due to error events in a cell stream transmitted as a plurality of cell sub-streams which includes the steps of receiving an incoming cell stream in the form of an ordered sequence of cells including payload cells, transmitting the incoming cell stream in a round robin fashion on a plurality of physical links such that the ordered sequence of cells is transmitted as a plurality of cell sub-streams, with each cell sub-stream having a multiplexed set of cells from the incoming cell stream, and inserting stuff (st) cells into the cell sub-streams so as to form continuous streams of data. Sequence number cells which are inserted periodically into each cell sub-stream, are used to align the cell sub-streams in frames. Sets of cell location information for the cell sub-streams are encoded and contain the location of payload cells and st cells located within a corresponding cell sub-stream.

Abstract: A method of monitoring the integrity of the path and flow of digital PCM data from a source end to a receiving end which includes generating a pseudo-random sequence of bits at the source end, transmitting the pseudo-random sequence of bits together with the PCM data through a transmission path to a receiving end, and applying the pseudo-random sequence of bits to a pseudo-random bit sequence checker at the receiving end.

Abstract: A phase detector for controlling a phase locked loop having a voltage controlled oscillator. A counter is clocked by a clock signal produced by the voltage controlled oscillator. A latch coupled to the counter is clocked by a modulated clock signal to latch values output by the counter. The modulated clock signal is produced by a phase modulator which modulates a synchronization clock reference signal. An accumulator coupled to the latch and clocked by the modulated clock signal receives and averages the latch values to produce a phase error signal representative of phase difference between the voltage controlled oscillator clock signal and the synchronization clock reference signal. The phase error signal is coupled to the voltage controlled oscillator to reduce the phase difference. The phase modulator modulates a rising edge of the synchronization clock reference signal with a modulation signal having modulation frequencies outside the loop bandwidth of the phase locked loop.

Abstract: According to the invention there is provided a method of signal coding that permits high speed data transmission over multiple pairs of UTP-5 cable from a transmission end to a receiving end which includes, at the transmission end, separating an incoming frame of data into a plurality of byte streams with a predefined sequence of bytes assigned to each of the streams, encoding every 2 bits of data in each stream into one of 4 logical voltage levels forming a symbol or quat thereby reducing the symbol or baud rate by 50% and inserting an escape sequence into one or more of the streams consisting of a sequence of zero's followed by a control code to indicate a transition from one state to another. At a receiving end, the method further includes reading the escape sequence and decoding the signals in accordance with the code contained in the escape sequence.

Abstract: A method of monitoring the integrity of the path and flow of digital PCM data from a source end to a receiving end which includes generating a pseudo-random sequence of bits at the source end, transmitting the pseudo-random sequence of bits together with the PCM data through a transmission path to a receiving end, and applying the pseudo-random sequence of bits to a pseudo-random bit sequence checker at the receiving end.

Abstract: An ATM layer device for interfacing between a physical layer device and an ATM switch, which includes means for prepending and postpending of switch routing information to cells destined to enter the switch and for removing such information from cells having left the switch

Abstract: An ATM inverse multiplexing cell-based system for reducing error-multiplication due to error events in the transmitted cell stream, which includes a first IMA assembly having an input coupled to an incoming cell stream from a first ATM layer device, a second IMA assembly having an output coupled to a second ATM layer device, a plurality of links coupling the first IMA assembly to the second IMA assembly. The first IMA assembly includes a multiplexer for multiplexing the incoming cell stream onto the plurality of links and for inserting onto the links framing cells in the form of "st" cells in place of idle cells and "S" cells to mark divisions in each channel corresponding to a given number of cells or a given time interval between successive "S" cells. An encoder encodes and inserts cell location information of both control cells and payload cells. The second IMA assembly includes a plurality of link buffers for receiving cells transmitted along respective ones of links.

Abstract: A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.