Patents by Inventor Kevin Iadonato
Kevin Iadonato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080059770Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.Type: ApplicationFiled: April 2, 2007Publication date: March 6, 2008Applicant: Transmeta CorporationInventors: Sanjiv Garg, Kevin Iadonato, Le Nguyen, Johannes Wang
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Publication number: 20070113214Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.Type: ApplicationFiled: January 10, 2007Publication date: May 17, 2007Applicant: Seiko Epson CorporationInventors: Kevin Iadonato, Le Nguyen
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Patent number: 7162616Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: GrantFiled: March 8, 2004Date of Patent: January 9, 2007Assignee: Renesas Technology America, Inc.Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Publication number: 20060123218Abstract: A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.Type: ApplicationFiled: January 25, 2006Publication date: June 8, 2006Applicant: Seiko Epson CorporationInventors: Kevin Iadonato, Trevor Deosaran, Sanjiv Garg
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Publication number: 20060041736Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.Type: ApplicationFiled: October 19, 2005Publication date: February 23, 2006Applicant: Transmeta CorporationInventors: Sanjiv Garg, Kevin Iadonato, Le Nguyen, Johannes Wang
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Publication number: 20060020773Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.Type: ApplicationFiled: September 27, 2005Publication date: January 26, 2006Applicant: Seiko Epson CorporationInventors: Trevor Deosaran, Sanjiv Garg, Kevin Iadonato
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Publication number: 20040172522Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: ApplicationFiled: March 8, 2004Publication date: September 2, 2004Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Patent number: 6772327Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: GrantFiled: May 9, 2002Date of Patent: August 3, 2004Assignee: Hitachi Micro Systems, Inc.Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Publication number: 20020174323Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: ApplicationFiled: May 9, 2002Publication date: November 21, 2002Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Patent number: 6418528Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: GrantFiled: August 10, 1998Date of Patent: July 9, 2002Assignee: Hitachi America, Ltd.Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Patent number: 5860000Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: GrantFiled: January 31, 1996Date of Patent: January 12, 1999Assignee: Hitachi Micro Systems, Inc.Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama