Patents by Inventor Kevin J. Hess
Kevin J. Hess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200248017Abstract: Resin compositions or formulations curable by UV or visible radiation have voltage-variable material (VVM) properties and/or electrical overstress (EOS) material properties. The resins may be used to construct or fabricate structures, articles, components, devices, or objects, either as standalone items or as a component(s) of larger structures or devices, using 3D printing or additive manufacturing (AM), such as in LED- or laser-based digital light projection (DLP) systems and laser-based stereolithography (SLA) systems. These items or components may be applicable for electrostatic dissipation, electrostatic discharge (ESD), or other EOS purposes.Type: ApplicationFiled: January 31, 2020Publication date: August 6, 2020Inventor: Kevin J. Hess
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Publication number: 20200032085Abstract: Elastomer-modified epoxy liquid resin compositions curable by UV radiation for cationic polymerization, in some embodiments curable at or approximately at 355 nm, or at shorter wavelengths, and preferably for use with 2D-exposure systems (e.g., DLP systems), which may be used for additive manufacturing (AM) or 3D printing. The compositions are mixtures or blends of epoxy with elastomers reactive with epoxy, such as polyurethane or polyurea. The resins may include acrylates as a minor component. The resins may generally have a wt % of epoxy that cures, and a wt % of an elastomer that is functionalized to form reactive species, and include a wt % of photoinitiator that degrades and forms an acid catalyst (a photoacid generator). Cured mechanical and thermal properties of the compositions may exhibit improved elasticity, impact resistance, and/or flexural modulus, depending on the weight ratio of epoxy resin to polyurethane or polyurea in the blend.Type: ApplicationFiled: July 29, 2019Publication date: January 30, 2020Inventor: Kevin J. Hess
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Patent number: 9331050Abstract: Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material.Type: GrantFiled: January 23, 2012Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kevin J. Hess, Chu-Chung Lee
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Patent number: 9331046Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: GrantFiled: June 26, 2014Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, James Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Patent number: 9099475Abstract: An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.Type: GrantFiled: September 12, 2012Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Michael B. McShane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Patent number: 9093429Abstract: A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.Type: GrantFiled: June 27, 2012Date of Patent: July 28, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Michael B. McShane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Patent number: 9082757Abstract: A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.Type: GrantFiled: October 31, 2013Date of Patent: July 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane, Tab A. Stephens
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Patent number: 9076664Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.Type: GrantFiled: October 7, 2011Date of Patent: July 7, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
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Publication number: 20150115463Abstract: A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Inventors: PERRY H. PELLEY, KEVIN J. HESS, MICHAEL B. MCSHANE, TAB A. STEPHENS
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Patent number: 8912667Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.Type: GrantFiled: January 31, 2012Date of Patent: December 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Robert J. Wenzel, Kevin J. Hess, Chu-Chung Lee
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Publication number: 20140308779Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chu-Chung LEE, Kian Leong CHIN, Kevin J. HESS, Patrick P. JOHNSTON, Tu-Anh N. TRAN, Heng Keong YIP
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Patent number: 8796822Abstract: A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.Type: GrantFiled: October 7, 2011Date of Patent: August 5, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
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Patent number: 8791582Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: GrantFiled: July 28, 2010Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Patent number: 8680674Abstract: A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.Type: GrantFiled: May 31, 2012Date of Patent: March 25, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Michael B. McShane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Publication number: 20140071652Abstract: An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: MICHAEL B. MCSHANE, KEVIN J. HESS, PERRY H. PELLEY, TAB A. STEPHENS
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Publication number: 20140001641Abstract: A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Inventors: MICHAEL B. MCSHANE, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Publication number: 20130320480Abstract: A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Inventors: Michael B. Mcshane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Patent number: 8501539Abstract: A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings.Type: GrantFiled: November 12, 2009Date of Patent: August 6, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Michael B. McShane
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Publication number: 20130193589Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Inventors: ROBERT J. WENZEL, Kevin J. Hess, Chu-Chung Lee
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Publication number: 20130087926Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane