Abstract: A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Abstract: A cyclic redundancy code generator for data packets without an inter-packet gap comprises a CRC generator which divides each packet by a generator polynomial of degree n wherein n and augmenting logic which divides, by the generator polynomial, the product of the intermediate remainder and the term of order n in the generator polynomial, whereby each packet is padded without zeros

Abstract: A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: A binary search tree including a multiplicity of nodes having pre-determined addresses and organised in a multiplicity of levels, and a hardware engine for the insertion of elements in the nodes. Being operable to make a search for the highest available node in a pattern in which all the nodes at each level beginning at the highest are searched before the search continues to the next lower level.

Abstract: A data bus system in which a read or write transaction includes an identification of the initiator of the transaction and optionally an identification of the transaction as a number in a cyclic progression and optionally a request for an acknowledgement.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths