Abstract: A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays.

Abstract: A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Abstract: A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays.

Abstract: A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Abstract: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized.