Patents by Inventor Kevin J. Kranzusch
Kevin J. Kranzusch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10310879Abstract: An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.Type: GrantFiled: October 10, 2011Date of Patent: June 4, 2019Assignee: NVIDIA CORPORATIONInventors: William J. Earl, Kevin J. Kranzusch, Satya Kiran Popuri, Christopher W. Johnson
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Publication number: 20130091500Abstract: An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.Type: ApplicationFiled: October 10, 2011Publication date: April 11, 2013Inventors: William J. Earl, Kevin J. Kranzusch, Satya Kiran Popuri, Christopher W. Johnson
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Patent number: 7903116Abstract: A graphics system adapts a performance level to be sufficient to maintain a performance criterion in an acceptable range. In one embodiment, at least one utilization parameter of the core clock domain and the memory clock domain is monitored. In response to detecting an over-utilization condition, the performance level is increased to maintain the desired minimum number of frames per second. In response to detecting an under-utilization condition, the performance level is decreased to reduce power consumption and increase the lifetime of the graphics system.Type: GrantFiled: October 27, 2003Date of Patent: March 8, 2011Assignee: Nvidia CorporationInventors: Michael M. Klock, Paul V. Puey, Paul E. Van Der Kouwe, Jeffrey M. Smith, Kevin J. Kranzusch
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Patent number: 7802147Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.Type: GrantFiled: December 13, 2007Date of Patent: September 21, 2010Assignee: NVIDIA CorporationInventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
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Patent number: 7627787Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.Type: GrantFiled: December 13, 2007Date of Patent: December 1, 2009Assignee: NVIDIA CorporationInventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
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Patent number: 7535433Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.Type: GrantFiled: May 18, 2006Date of Patent: May 19, 2009Assignee: NVIDIA CorporationInventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch
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Patent number: 7444551Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.Type: GrantFiled: December 16, 2002Date of Patent: October 28, 2008Assignee: NVIDIA CorporationInventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
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Patent number: 7382366Abstract: Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parameters.Type: GrantFiled: October 21, 2003Date of Patent: June 3, 2008Assignee: NVIDIA CorporationInventors: Michael M. Klock, Jeffrey M. Smith, Satish D. Salian, Kevin J. Kranzusch
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Publication number: 20080028181Abstract: Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.Type: ApplicationFiled: March 21, 2007Publication date: January 31, 2008Applicant: NVIDIA CorporationInventors: Peter C. Tong, Sonny S. Yeoh, Kevin J. Kranzusch, Gary D. Lorensen, Kaymann L. Woo, Ashish Kishen Kaul, Colyn S. Case, Stefan A. Gottschalk, Dennis K. Ma
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Publication number: 20070268296Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Inventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch