Abstract: A method of controlling access to a model specific register of a microprocessor. A method of controlling access to a model specific register of a processor having a normal execution mode and a secure execution mode may include storing processor state and mode information in the model specific register. Further, the method may include protection logic allowing a software invoked write access to modify the information within the model specific register during the normal execution mode. The method may further include security logic selectively inhibiting the software invoked write access during the secure execution mode.

Abstract: A processor changes the mapping of register addresses to registers dependent on an instruction field. In one particular embodiment, the mapping may be changed for byte addressing of the registers. A register mapping in which each register address maps to either the least significant byte or the next least significant byte of a subset of the registers may be supported, as well as a register mapping in which each register address maps to the least significant byte of each register, in one implementation. In one particular implementation, the instruction field may be a prefix field (e.g. a prefix byte). The processor may provide for uniform addressing of registers (e.g. byte addressing of the registers) responsive to a prefix field, in other embodiments, irrespective of the addressing provided if the prefix field is not included, or is encoded differently than the encoding which results in the uniform addressing.

Abstract: A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).

Abstract: A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an indication within the mask corresponds to each of a plurality of flags used by the processor. Based on the state of the indication, the processor may clear a corresponding flag or may retain the value of the corresponding flag. By programming the register appropriately, the desired clearing and retaining of the plurality of flags may be performed as part of the system call instruction. Flexibility may be provided for different operating systems having different sets of flags to be preserved or cleared.

Abstract: A processor is described which executes an instruction defined to swap the contents of at least one special purpose register (e.g. an MSR or a segment register) and another register. In some implementations, both of the registers are special purpose registers (e.g. a segment register and an MSR). The instruction may be used to provide a pointer to an operating system data structure in a register useable for address generation, and to preserve the content of that register in the other register involved in the swap. For example, in the segment register/MSR embodiment, the MSR may store the pointer and the segment register base address may be used in address generation operations.

Abstract: A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.

Abstract: A processor includes multiple protected operating modes. In at least one of the protected operating modes, segmentation is disabled or partially disabled. In other words, segment descriptor information may not affect the execution of an instruction specifying the segment register storing the segment descriptor information. In other protected operating modes, segmentation may not be disabled (e.g. segment descriptor information does affect the execution of the instruction specifying the segment register storing the segment descriptor information). However, segment load instructions may be performed in any protected operating mode (including checking segment descriptors for exception conditions during the segment load), which may allow a code sequence executing in one of the protected operating modes in which segmentation is disabled to establish segments in the segment registers for use by other code sequences executing in other protected operating modes.

Abstract: A processor executes a system call instruction. The processor includes at least two registers in which target addresses may be stored, and selects the target address from one of the registers responsive to the operating mode. Different target addresses may be programmed into the registers, and thus the operating mode of the code sequence may be indicated by which target address is selected.

Abstract: A processor supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction and/or operand may be indicated by a segment selector or pointer or by a pointer only.

Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

Abstract: The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

Abstract: A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length.

Abstract: A processor, apparatus and method for storing segment descriptors of different sizes in a segment descriptor table are disclosed. Smaller segment descriptors may be segment descriptors similar to the x86 architecture definition, and larger segment descriptors may be used to provide virtual addresses (e.g. base addresses or offsets) having more the 32 bits. By providing a segment descriptor table that stores different sized segment descriptors, maintaining multiple segment descriptor tables for different operating modes may be avoidable while providing support for segment descriptors having addresses greater than 32 bits. In one embodiment, the larger segment descriptors may be twice the size of the smaller segment descriptors. The segment descriptor table may comprise entries, each capable of storing the smaller segment descriptor, and a larger segment descriptor may occupy two entries of the table.

Abstract: A processor supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used. In the unsegmented address space, a canonical check applies to addresses. In the segmented address space, a segment limit check applies. In some cases, both a segment limit check and a canonical check applies dependent on the segment used (e.g. either user or table segments). An exception circuit selects one or more of the canonical check result(s) and the segment limit check result to generate an exception indication. The selection is dependent on the operating mode and the segment of the data reference. The processor may also perform selective truncation of addresses based on the operating mode and the segment.

Abstract: A processor changes the mapping of register addresses to registers dependent on an instruction field. In one particular embodiment, the mapping may be changed for byte addressing of the registers. A register mapping in which each register address maps to either the least significant byte or the next least significant byte of a subset of the registers may be supported, as well as a register mapping in which each register address maps to the least significant byte of each register, in one implementation. In one particular implementation, the instruction field may be a prefix field (e.g. a prefix byte). The processor may provide for uniform addressing of registers (e.g. byte addressing of the registers) responsive to a prefix field, in other embodiments, irrespective of the addressing provided if the prefix field is not included, or is encoded differently than the encoding which results in the uniform addressing.

Abstract: A processor supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction and/or operand may be indicated by a segment selector or pointer or by a pointer only.

Abstract: A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e.g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e.g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacements were expanded, and flexibility in the placement of variables in memory may be achieved. For example, static variables may be placed in memory with flexibility, and IP relative addressing may be used to locate the static variables.

Abstract: A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table.

Abstract: An apparatus and method for generating 64 bit displacement and immediate values. In a given processor architecture such as the x86 architecture, instructions may conform to a specified instruction format. The instruction format can include a displacement field and an immediate field. The displacement field can include a displacement value of up to 32 bits and the immediate field can include an immediate value of up to 32 bits. In order to generate 64 bit displacement and immediate values, the 32 bit value from the displacement field of an instruction and the 32 bit value from the immediate field of the instruction may be concatenated to generate a 64 bit concatenated value. The concatenated value may be used by an execution core as a 64 bit displacement or immediate value as specified by the instruction.

Abstract: Various methods and systems for mapping virtual addresses having more than 32 bits, such as 48 or 64 bits, to physical addresses are disclosed. A processor includes a translation unit that translates or maps a virtual address to a physical address. The translation unit may translate a virtual address to a physical address using either a first or second mapping mechanism (e.g., a first or second plurality of paging tables, with entries respectively having first and second sizes) supporting virtual addresses having at most a first number of bits, such as 32 bits, or a third page mapping mechanism (e.g., a third plurality of page tables) supporting virtual address having more than the first number of bits, such as 48 bits or 64 bits. The translation unit may select the first or second plurality of paging tables depending on the active operating mode of the processor.