Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

Abstract: A static pulse bus circuit and method having dynamic power supply rail selection reduces static and dynamic power consumption over that of static pulse bus designs with fixed power supply rail voltages. Every other (even) bus repeater is operated with a selectable power supply rail voltage that is selected in conformity with a state of the input signal of the bus repeater. The odd bus repeaters are operated from the lower of the selectable power supply voltages supplied to the even repeaters. The odd bus repeaters may also be operated from a selectable power supply rail voltage opposite the selectable-voltage power supply rail provided to the even bus repeaters, in which case the opposing rail of the even bus repeaters is set to the higher of the voltages selectable in the odd bus repeaters.

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

Abstract: A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

Abstract: Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials of the power supply from circuitry with large high leakage devices. Driver circuits comprise a low leakage logic path for holding logic states of the output. A high leakage logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each high leakage path that enhances the current drive of a logic state on the output are leakage stress relieved by allowing their drive inputs to collapse after the output logic state has been asserted. The high leakage logic paths employ multiple stages with collapsing logic states that are generated in response to asserted logic states on the output and logic states of the low leakage logic path thus reducing the device sizes needed to control leakage.

Abstract: CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where circuitry does not have power supply gating. Each output that couples signals from one logic circuit domain to another logic circuit is interfaced with a C_driver and a S_keeper which automatically assure that the output state is held when circuitry is power-gated put to reduce leakage power. The S_keeper and C_driver have low leakage circuits that maintain signal states and are not used for high speed operation.

Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.

Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

Abstract: Circuits within a logic domain use partitioned power supply buses. Selected of the power supply buses are coupled to the power supply voltage potentials with electronic switches with gradated conductivity and leakage current. When the circuits are actively switching during a logic operation, the power supply voltage potentials are coupled to the buses with maximum conductivity. At predetermined times later, selected of the electronic switches are switched OFF to reduce leakage current. Lower conductivity and thus lower leakage switches remain ON to ensure corresponding logic states are maintained during a controlled low leakage time period. Various logic configurations are used to switch OFF high leakage devices.

Abstract: A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters.

Abstract: A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.

Abstract: An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A compressor array generates a previous accumulated carry-save sum. A three-input/two-output carry-save adder pre-reduces the constant value row and the previously accumulated carry-save sum into a two-row intermediate carry-save sum that is added to the partial product matrix to form a current accumulated carry-save sum.

Abstract: An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.

Abstract: A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.

Abstract: An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.

Abstract: A method and apparatus performing rotate operations using cascaded multiplexers provides a scalable rotator circuit having a sub-field rotate capability that requires no additional interconnects at the sub-field endpoints. The rotator performs bit field swap operations at each stage of a series of cascaded multiplexers. The bit field size increases monotonically from a single bit to half of the rotator operand size. The control logic selects swap operations for each individual bit field at each stage, in order to arrange a desired rotated output vector.

Abstract: A method and apparatus for testing pipelined dynamic logic makes it possible to set and retrieve values from dynamic logic pipelines that have no internal latches. A modification to the pipeline circuits and clocking circuitry enable scanning logic to set and retrieve values from the pipelined circuits.

Abstract: An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A compressor array generates a previous accumulated carry-save sum. A three-input/two-output carry-save adder pre-reduces the constant value row and the previously accumulated carry-save sum into a two-row intermediate carry-save sum that is added to the partial product matrix to form a current accumulated carry-save sum.