Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: Labels for a garment include a fabric first label with brand indicia woven therein for attachment to the garment and a fabric second label with content indicia printed thereon for attachment to the garment. The printed content indicia has an appearance of being woven like the woven brand indicia. The content indicia is preferably printed in a font having an appearance similar to alphanumeric characters of the woven brand indicia. The font preferably resembles a thread pattern of the alphanumeric characters of the woven brand indicia.

Abstract: Labels for a garment include a fabric first label with brand indicia woven therein for attachment to the garment and a fabric second label with content indicia printed thereon for attachment to the garment. The printed content indicia has an appearance of being woven like the woven brand indicia. The content indicia is preferably printed in a font having an appearance similar to alphanumeric characters of the woven brand indicia. The font preferably resembles a thread pattern of the alphanumeric characters of the woven brand indicia.

Abstract: A biology assembly for educating and demonstrating a biological process. The assembly is comprised of a treated grid formed from a fiberglass mesh. The mesh is then dipped into a nutrient agar. The nutrient may be adjusted to accommodate the microbe being grown. Test chemicals may also be added.

Abstract: An apparatus for treating contaminated, e.g. oily, water including a floating skimmer (3) for skimming the surface of the contaminated water (2). The contaminated water from the skimmer is fed to a hydrocyclone (6) for separation of the water and contaminant. The hydrocarbon rich stream from the hydrocyclone undergoes further separation using a spear (8).

Abstract: The present invention relates to a hydrocyclone apparatus which is simple in design, more space efficient, and easier to maintain than prior art designs. The invention comprises a three chamber vessel wherein the inlet chamber is between the outlet and overflow chambers. Therefore, the inlets to the liners are between the plates dividing the vessel into separate chambers and the outlets from the liners extend directly into the end chambers the labyrinth of passages and conduits for the overflow liquid. The present invention includes a no bolt securing arrangement for securing the liners in the vessel. In particular, the liner includes a shoulder portion which abuts one of the dividing plates and an end cap which closes the open end of the vessel being in close proximity to the ends of the liners thereby securing the liners in the opening in the dividing plates. The shoulder further includes lobes to limit rotation of the shoulders.

Abstract: The invention provides a highly space efficient solution to designing hydrocyclone vessels and the liners that are used therein. Moreover, the invention reduces the maintenance requirements for the vessels by providing the liners as units which are preassembled outside the vessel and installed in and out of the vessel without bolts or other minimally detailed process. The invention primarily includes a three chamber vessel wherein the inlet chamber is between the outlet and reject chambers. Therefore the inlet to the liners is between the plates dividing the chamber into separate chambers and the outlets from the liners extend straight into the end chambers. This avoids having to provide conduits from the reject end of the liner to a reject gallery in the plate or outside the vessel. Secondly, the design incorporated a no bolt design to secure the involute inlet into the liner and secure the liner into the opening in the plate.

Abstract: A paint tray for applying paint to a roller, said tray comprising a circular well of sufficient diameter to receive a paint roller within it, a spreading surface sloping slightly upwardly and outwardly from said well to a circular lip and a support means to support the tray on a flat surface.

Abstract: A disk control system offloads to the disk controller much of the overhead associated with disk operations and makes the CPU available for other work. A command block that fully specifies a user request for a disk operation is forwarded to the disk memory unit. The command block contains a unique identifier for tracking of user requests. User requests are executed by the disk memory unit in an order that is most efficient for the disk drive system. The status of a user request is communicated to the CPU via an interrupt and a status block containing the unique identifier. The status block indicates status conditions such as command read, completion and DMA channel request. The disk driver contains a work queue for user requests that have not been forwarded to the disk memory unit and a pending queue for user requests that are awaiting completion by the disk memory unit. By manipulation of the work queues and pending queues, the disk controller can be automatically reinitialized when an error occurs.