Patents by Inventor Kevin J. Osugi

Kevin J. Osugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit and method for performing multiple modulo mathematic operations
    Patent number: 8090757
    Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 3, 2012
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Richard J. Takahashi, Kevin J. Osugi
  • Circuit and method for performing multiple modulo mathematic operations
    Publication number: 20090106342
    Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.
    Type: Application
    Filed: November 27, 2007
    Publication date: April 23, 2009
    Applicant: ITT Manufacturing Enterprises, Inc.
    Inventors: Richard J. Takahashi, Kevin J. Osugi
  • Circuit and method for performing multiple modulo mathematic operations
    Patent number: 7320015
    Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: January 15, 2008
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Richard J. Takahashi, Kevin J. Osugi
  • Circuit and method for performing multiple modulo mathematic operations
    Patent number: 6973470
    Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: December 6, 2005
    Assignee: Corrent Corporation
    Inventors: Richard J. Takahashi, Kevin J. Osugi
  • Circuit and method for performing multiple modulo mathematic operations
    Publication number: 20020194237
    Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.
    Type: Application
    Filed: October 4, 2001
    Publication date: December 19, 2002
    Inventors: Richard J. Takahashi, Kevin J. Osugi
  • Hardware graphics accelerator system and method therefor
    Patent number: 5678037
    Abstract: A hardware graphics accelerator (HGA) system which has a source memory element which is loaded to initiate HGA operations operates in two modes: (1) a FIFO mode for normal HGA operations and (2) a recirculate mode for high speed pattern transfers and pattern expands by the HGA. The use of the second mode simplifies the structure and increases the operating speed of the HGA and its associated CPU by eliminating the use of the dedicated pattern registers and pattern control multiplexers of prior art HGA systems.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: October 14, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Kevin J. Osugi, Darrell J. Starnes