Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip.

Abstract: A signal state management (SSM) system avoids both the overhead of maintaining call state and complex signaling in a packet network gateway, while simultaneously providing a more scalable system by not placing too great a state or processing burden on the signaling or call processing server. The SSM system sends an event/action table from a call agent to the gateway that directs the gateway to detect and accumulate specified signaling events generated by a telephone. The gateway accumulates the signaling events according to the event/action table and notifies the call agent only when the signaling events specified in the event/action table are detected. The call agent then sends a new event/action table to the gateway that commands the gateway to detect and accumulate a new set of signaling events. After notifying the call agent, the gateway operates in a quarantine where all signaling events are queued.

Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip.

Abstract: A signal state management (SSM) system avoids both the overhead of maintaining call state and complex signaling in a packet network gateway, while simultaneously providing a more scalable system by not placing too great a state or processing burden on the signaling or call processing server. The SSM system sends an event/action table from a call agent to the gateway that directs the gateway to detect and accumulate specified signaling events generated by a telephone. The gateway accumulates the signaling events according to the event/action table and notifies the call agent only when the signaling events specified in the event/action table are detected. The call agent then sends a new event/action table to the gateway that commands the gateway to detect and accumulate a new set of signaling events. After notifying the call agent, the gateway operates in a quarantine where all signaling events are queued.

Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip.

Abstract: A signal state management (SSM) system avoids both the overhead of maintaining call state and complex signaling in a packet network gateway, while simultaneously providing a more scalable system by not placing too great a state or processing burden on the signaling or call processing server. The SSM system sends an event/action table from a call agent to the gateway that directs the gateway to detect and accumulate specified signaling events generated by a telephone. The gateway accumulates the signaling events according to the event/action table and notifies the call agent only when the signaling events specified in the event/action table are detected. The call agent then sends a new event/action table to the gateway that commands the gateway to detect and accumulate a new set of signaling events. After notifying the call agent, the gateway operates in a quarantine where all signaling events are queued.

Abstract: A memory controller and system for providing access to PCMCIA standard memory cards and non-standard memory cards. Non-standard memory cards are memory cards that are compliant with PCMCIA standards for sockets and are non-compliant in other respects. The memory controller has a register for storing a code that indicates whether a memory card is a PCMCIA card or a non-standard memory card. An access control circuit in the memory controller activates and deactivates memory card control signals at times required by the memory card and as indicated by the memory card type. An acknowledge control circuit generates an acknowledge signal to a requesting processor at a time prescribed by the type of memory card.

Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip.

Abstract: A computing system, having an input/output bus for communicating data thereon, is connected to a network by a pair of network controller devices. Each of the network controller devices, in turn, connect to a corresponding one of a pair of multi-ported network repeater elements which are, in turn, connected to one another by a pair of network links. At least one workstation is connected to each of the network repeaters. One of the network controllers is initially selected as a primary data communicating path from the computing system to the network. The network controllers periodically transmit messages to one another, and if receipt of those messages by the primary network controller is noted, the selection of the primary controller will be switched to the other.