Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.

Abstract: A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.

Abstract: A routing switch includes a first router module having N1 signal input terminals, M1 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N1 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the N1 signal output terminals. The router further includes a second router module having N2 signal input terminals, M2 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N2 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the M2 signal output terminals.

Abstract: A circuit for processing a differential serial digital data signal provided by a signal source includes a transmission line and an amplifier. A first capacitor couples a first conductor of the transmission line to a first input of the amplifier and a second capacitor couples a second conductor of the transmission line to a second input of the amplifier, and a termination resistor is connected between the first and second inputs of the amplifier. The capacitance value of the first capacitor is such that the time constant of the first capacitor and the termination resistor is about one-third of one bit time of the serial digital data signal and the capacitance value of the second capacitor is substantially greater than the capacitance value of the first capacitor.

Abstract: Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.

Abstract: Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.

Abstract: A digital audio receiver with multi-channel swapping capabilities receives as inputs at least two AES serial digital audio streams. The audio streams are decoded, and each audio channel is stored in a separate buffer. The outputs of the buffers are input to at least two selectors. The selectors under user control select for each output digital audio stream which channels are represented. The recombined digital audio streams are then input to a conventional router cross-point matrix for directing to a desired destination and formatted into new AES serial digital audio streams.

Abstract: A system and method for synchronous switching of digital audio data channels while maintaining block alignment between the switched digital audio signals at an output separates status and user bits from audio data and validity bits for each digital audio signal, storing the status and user bits in respective memories for each digital audio data channel. The audio data and validity bits for each digital audio data channel are input via a data first-in, first-out buffer to an audio multiplexer. The status and user bits from the memories for each digital audio data channel are read out by a system clock in synchronization with a system block signal and input to a status/user multiplexer. A selector provides control signals to the multiplexers to select the digital audio data channel to provide to an output transmitter.

Abstract: A system for switching video of two different standards that uses a single crosspoint matrix and a single local controller coupled to two memory blocks for storage of crosspoint selection data. The crosspoint selection data is written to the crosspoint matrix according to the video reference signals that correspond to the crosspoint selection data to be written. Switching of the crosspoints then occurs according to the video reference signal corresponding to the crosspoints to be switched.

Abstract: A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.

Abstract: A crosstalk reduction circuit compensates for input to output capacitance coupling of each switch of a crosspoint matrix and for output to common level capacitance coupling for each integrated circuit chip that makes up the crosspoint matrix. Each input signal to the crosspoint matrix is capacitively scaled, summed and inverted to produce an "off" isolation compensation signal, and each output signal from the crosspoint matrix is capacitively scaled, summed and inverted to produce an output isolation compensation signal. Each compensation signal is resistively scaled for each output signal, and the scaled compensation signals are subtracted from the output signals to reduce the crosstalk in the output signals.