Patents by Inventor Kevin Jang

Kevin Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11853130
    Abstract: A linked hinge mechanism includes a first member, a second member, a hinge unit and a passive unit. The hinge unit is connected to the first member and the second member, wherein the first member is adapted to be rotated relative to the second member via the hinge unit. The passive unit is adapted to be moved by the movement of the hinge unit, wherein the passive unit is adapted to be rotated by the movement of the hinge unit in only a portion of the whole rotation range of the hinge unit.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: December 26, 2023
    Assignee: WISTRON CORP.
    Inventors: Kuan-Te Yu, Chia-Lian Yen, Po-Han Huang, Kevin Jang, Chih-Sheng Chou
  • Publication number: 20220147112
    Abstract: A linked hinge mechanism includes a first member, a second member, a hinge unit and a passive unit. The hinge unit is connected to the first member and the second member, wherein the first member is adapted to be rotated relative to the second member via the hinge unit. The passive unit is adapted to be moved by the movement of the hinge unit, wherein the passive unit is adapted to be rotated by the movement of the hinge unit in only a portion of the whole rotation range of the hinge unit.
    Type: Application
    Filed: March 5, 2021
    Publication date: May 12, 2022
    Inventors: Kuan-Te YU, Chia-Lian YEN, Po-Han HUANG, Kevin JANG, Chih-Sheng CHOU
  • Patent number: 8841727
    Abstract: A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 23, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andrew Walker, Helmut Puchner, Sai Dhanraj, Kevin Jang
  • Patent number: 8283727
    Abstract: A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 9, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andrew Walker, Helmut Puchner, Sai Dhanraj, Kevin Jang
  • Patent number: 8143673
    Abstract: A circuit with electrostatic discharge protection is described. The circuit includes an output driver transistor with an extended drain contact region. The circuit also includes a distinct device configured to provide electrostatic discharge protection for the output driver transistor. The distinct device includes an electrostatic discharge protection transistor with an extended drain region.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: March 27, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andrew Walker, Helmut Puchner, Kevin Jang
  • Patent number: 7768068
    Abstract: A semiconductor topography and a method for forming a drain extended metal oxide semiconductor (DEMOS) transistor is provided. The semiconductor topography includes at least a portion of an extended drain contact region formed within a well region and a plurality of dielectrically spaced extension regions interposed between the well region and a channel region underlying a gate structure of the topography. The channel region of a first conductivity type and the well region of a second conductivity type opposite of the first conductivity type. In addition, the plurality of dielectrically spaced extension regions and the extended drain contact region are of the second conductivity type. Each of the plurality of dielectrically spaced extension regions has a lower net concentration of electrically active impurities than the well region. Moreover, the extended drain contact region has a greater net concentration of electrically active impurities than the well region.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 3, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kevin Jang, Bill Phan, Helmut Puchner
  • Publication number: 20050100781
    Abstract: This invention provides an actively controlled electrochemical cell and a smart battery containing such a cell with a programmed-timing activation capability. As a preferred embodiment, the cell includes (a) a cathode, an anode, a porous separator electronically insulating the cathode from the anode, and an electrolyte, wherein the anode is initially isolated from the electrolyte fluid prior to the first use of the cell; (b) an actuator in actuation relation to the electrolyte or the anode; and (c) a control device in control relation to the actuator for sending programmed signals to the actuator to activate the cell by allowing a desired amount of an active anode material at a time to be exposed to the electrolyte during the first use and/or successive uses of the cell. The cell or battery has an essentially infinite shell life and an exceptionally long operating life.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 12, 2005
    Inventors: Kevin Jang, Wen Huang