Patents by Inventor Kevin Jia

Kevin Jia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11115036
    Abstract: An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 7, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Shitong Zhao, Kevin Jia-Nong Wang, Shyam Sivakumar, Debesh Bhatta
  • Patent number: 10958279
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: March 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Debesh Bhatta, Kevin Jia-Nong Wang, Karthik Nagarajan, John Abcarius, Andrew Weil, Christian Venerus, Jeffrey Mark Hinrichs
  • Publication number: 20210075434
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Inventors: Debesh BHATTA, Kevin Jia-Nong WANG, Karthik NAGARAJAN, John ABCARIUS, Andrew WEIL, Christian VENERUS, Jeffrey Mark HINRICHS
  • Patent number: 10867284
    Abstract: A machine may be configured to generate recruitment leads based on targeted content. For example, the machine causes a presentation of an item of digital media in a user interface of a first device associated with a member of a social networking service. The member may be targeted for the presentation of the item of digital media. The machine, based on the presentation of the item to the member, accesses an event message pertaining to an interaction by the member with the item of digital media. The machine, based on the event message, identifies an indication of interest by the member in a content of the item. The machine generates a communication pertaining to the interest by the member in the content of the item. The machine transmits the communication to a second device associated with a recruiter.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 15, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lanhui Long, Kevin Jia, Kathleen Garvey, Raviraj Jain, William Tang
  • Patent number: 10615808
    Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Kevin Jia-Nong Wang, Shyam Sivakumar
  • Publication number: 20200106446
    Abstract: This disclosure provides a method and apparatus for a temperature-compensated oscillator. In some example implementations, the temperature-compensated oscillator may include a first oscillator, a second oscillator, and a temperature compensation block. The first oscillator may generate a first periodic clock signal and the second oscillator may generate a second periodic clock signal. The temperature-compensating block may generate a compensation signal based on the first period clock signal and the second periodic clock signal.
    Type: Application
    Filed: June 25, 2019
    Publication date: April 2, 2020
    Inventors: Shyam SIVAKUMAR, Kevin Jia-Nong WANG, Anish CHIVUKULA
  • Publication number: 20200091918
    Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Kevin Jia-Nong Wang, Shyam Sivakumar
  • Patent number: 10539470
    Abstract: A sub-threshold MOSFET temperature sensor is provided in which a sub-threshold leakage current through a sub-threshold transistor having its source connected to its gate is mirrored through a diode-connected transistor to produce an output voltage. Feedback maintains a drain voltage for the sub-threshold transistor to equal the output voltage.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Kevin Jia-Nong Wang
  • Patent number: 10374651
    Abstract: An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: August 6, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shyam Sundar Sivakumar, Kevin Jia-Nong Wang
  • Publication number: 20190120699
    Abstract: A sub-threshold MOSFET temperature sensor is provided in which a sub-threshold leakage current through a sub-threshold transistor having its source connected to its gate is mirrored through a diode-connected transistor to produce an output voltage. Feedback maintains a drain voltage for the sub-threshold transistor to equal the output voltage.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 25, 2019
    Inventor: Kevin Jia-Nong Wang
  • Patent number: 10269490
    Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kevin Jia-Nong Wang, Chao Song
  • Publication number: 20180315548
    Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.
    Type: Application
    Filed: August 25, 2017
    Publication date: November 1, 2018
    Inventors: Kevin Jia-Nong WANG, Chao SONG
  • Publication number: 20170147983
    Abstract: A machine may be configured to generate recruitment leads based on targeted content. For example, the machine causes a presentation of an item of digital media in a user interface of a first device associated with a member of a social networking service. The member may be targeted for the presentation of the item of digital media. The machine, based on the presentation of the item to the member, accesses an event message pertaining to an interaction by the member with the item of digital media. The machine, based on the event message, identifies an indication of interest by the member in a content of the item. The machine generates a communication pertaining to the interest by the member in the content of the item. The machine transmits the communication to a second device associated with a recruiter.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: Lanhui Long, Kevin Jia, Kathleen Garvey, Raviraj Jain, William Tang
  • Patent number: 6697004
    Abstract: A novel mismatched-shaping DAC architecture is described. The inventive DAC partially spectrally shapes data conversion errors. In accordance with the present invention, the DAC mismatch-shaping function is fully effective for input signal amplitude levels that are relatively low (i.e., close to mid-scale), however, the mismatch-shaping function is not fully effective for input signal amplitude levels that are relatively high. This results in the simplification in complexity, reduced power dissipation, and shortened propagation delays associated with the mismatch-shaping DAC digital logic circuitry. Exemplary delta-sigma ADC and DAC architectures adapted for use with the present inventive partial mismatch-shaping DAC are also described.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: February 24, 2004
    Assignee: Silicon Wave, Inc.
    Inventors: Ian Andrew Galton, Jorge Alberto Grilo, Kevin Jia-Nong Wang