Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

Abstract: Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A first waveguide core includes first and second sections. A second waveguide core includes a first section laterally adjacent to the first section of the first waveguide core and a second section laterally adjacent to the second section of the first waveguide core. An interconnect structure is formed over the first waveguide core and the second waveguide core. The interconnect structure includes first and second transmission lines. The first transmission line is physically connected within the interconnect structure to the first section of the first waveguide core. The second transmission line includes a first section physically connected within the interconnect structure to the second section of the first waveguide core and a second section adjacent to the first transmission line.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a dielectric layer including an edge, a waveguide core region on the dielectric layer, and multiple segments on the dielectric layer. The waveguide core region has an end surface, and the waveguide core region is lengthwise tapered toward the end surface. The segments are positioned between the waveguide core region and the edge of the dielectric layer. A waveguide core has a section positioned over the waveguide core region in an overlapping arrangement. The waveguide core has an end surface, and the section of the waveguide core is lengthwise tapered toward the end surface.

Abstract: A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

Abstract: A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

Abstract: Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A first waveguide core includes first and second sections. A second waveguide core includes a first section laterally adjacent to the first section of the first waveguide core and a second section laterally adjacent to the second section of the first waveguide core. An interconnect structure is formed over the first waveguide core and the second waveguide core. The interconnect structure includes first and second transmission lines. The first transmission line is physically connected within the interconnect structure to the first section of the first waveguide core. The second transmission line includes a first section physically connected within the interconnect structure to the second section of the first waveguide core and a second section adjacent to the first transmission line.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a dielectric layer including an edge, a waveguide core region on the dielectric layer, and multiple segments on the dielectric layer. The waveguide core region has an end surface, and the waveguide core region is lengthwise tapered toward the end surface. The segments are positioned between the waveguide core region and the edge of the dielectric layer. A waveguide core has a section positioned over the waveguide core region in an overlapping arrangement. The waveguide core has an end surface, and the section of the waveguide core is lengthwise tapered toward the end surface.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: Structures for a filter and methods of fabricating a structure for a filter. The filter is coupled to a waveguide core. The filter includes a first plurality of grating structures positioned adjacent to a first section of the waveguide core and a second plurality of grating structures positioned adjacent to a second section of the waveguide core. The first plurality of grating structures are configured to cause laser light in a first portion of a wavelength band to be transferred between the first section of the waveguide core and the first plurality of grating structures. The second plurality of grating structures are configured to cause laser light in a second portion of a wavelength band to be transferred between the second section of the waveguide core and the second plurality of grating structures.

Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Abstract: Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.