Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

Abstract: A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.

Abstract: A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Abstract: A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeeding pulses of the input output signal. In an enhancement, the system may also have a missing pulse detector which is operable to compare a current interval with a parameter to determine whether a pulse is missing in the input signal.

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Abstract: A serial peripheral interface (SPI) module includes a transceiver including a clock line, a data line and at least one slave select line. The module also includes an interface circuit configured to monitor the slave select line and assert a fault based upon an incorrect de-assertion of the slave select line.

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.

Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.