Patents by Inventor Kevin Kolvenbach
Kevin Kolvenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9453873Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.Type: GrantFiled: January 14, 2014Date of Patent: September 27, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Fen Chen, Roger A. Dufresne, Kevin Kolvenbach, Michael A. Shinosky
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Patent number: 9153558Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: GrantFiled: August 2, 2012Date of Patent: October 6, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Publication number: 20150198654Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Fen Chen, Roger A. Dufresne, Kevin Kolvenbach, Michael A. Shinosky
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Publication number: 20120292763Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: ApplicationFiled: August 2, 2012Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Patent number: 8304863Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: GrantFiled: February 9, 2010Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Publication number: 20110193199Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Patent number: 7805274Abstract: A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (?T value) is determined for the given device based on the poly-gate temperature and the channel temperature.Type: GrantFiled: November 13, 2006Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Paul A. Hyde, Kevin Kolvenbach, Giuseppe La Rosa
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Patent number: 7710141Abstract: A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.Type: GrantFiled: January 2, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Giuseppe La Rosa, Kevin Kolvenbach, Ping-Chuan Wang, Stephen D. Wyatt
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Publication number: 20090167336Abstract: A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.Type: ApplicationFiled: January 2, 2008Publication date: July 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giuseppe La Rosa, Kevin Kolvenbach, Ping-Chuan Wang, Stephen D. Wyatt
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Publication number: 20080112458Abstract: A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (?T value) is determined for the given device based on the poly-gate temperature and the channel temperature.Type: ApplicationFiled: November 13, 2006Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ping-Chuan Wang, Paul A. Hyde, Kevin Kolvenbach, Giuseppe La Rosa
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Publication number: 20070235769Abstract: A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.Type: ApplicationFiled: February 1, 2006Publication date: October 11, 2007Applicant: International Business Machines CorporationInventors: Giuseppe La Rosa, Kevin Kolvenbach, John Massey, Ping-Chuan Wang, Kai Xiu
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Patent number: 6476632Abstract: A method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor is described.Type: GrantFiled: June 22, 2000Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Gluseppe La Rosa, Fernando Guarin, Kevin Kolvenbach, Stewart Rauch, III