Abstract: A spatial light modulator (10) with a programmable format pixel array (14). The pixel array (14) has a programmable row address circuit (30), and a partitionable programmable column data loading circuit (32) which permits the array (14) to be operated in multiple formats compatible with NTSC, PAL, SECAM and other broadcasting standards. The pixel array (14) is of the DMD type. The array can be configured as 864.times.576 pixel array, a 768.times.576 pixel array, an 864.times.480 pixel array, or a 640.times.480 pixel array. This format is controlled by hardware (30,32) designed into the DMD chip. A partitionable shift register (32) has a MUXED input to provide testability, permitting some or all of the data input lines (D0-D53) to be utilized, and also allowing pixel data to be loaded back into the shift register (32) for functional verification. A programmable row address circuit (30) automatically addresses a subset of pixel rows as a function of a single input.

Abstract: An electronic storage buffer (22) is efficiently used by dividing the buffer into a first (26) and second (28) storage area with a dynamically adjustable boundary (24) governing the respective sizes of each storage area. If the first storage area becomes full with data, the first storage area can be expanded and the second storage area can be reduced to utilize the empty space in the second storage area. Conversely, the second storage area can be expanded and the first storage area can be reduced to satisfy the data storage demands of the second storage area.

Abstract: A method and device for controlling the bias voltages for a split-reset spatial light modulator. Each block of the spatial light modulator can be individually controlled lowering the throughput needed to load each frame of data. Blocks are selected individually or in groups with the potential of providing one voltage condition on the selected blocks and a different voltage condition on the deselected blocks. One embodiment of the disclosed method comprises input latches and buffers 44, address decode logic 46 to determine the selected blocks, mode select logic 48 to determine the requested operation, delay circuitry 50 to minimize current loading, and level shifters 52 to convert logic signals to voltage levels appropriate to control the output drive circuitry 54.

Abstract: A method and device for controlling the bias voltages for a split-reset spatial light modulator. Each block of the spatial light modulator can be individually controlled lowering the throughput needed to load each frame of data. Blocks are selected individually or in groups with the potential of providing one voltage condition on the selected blocks and a different voltage condition on the deselected blocks. One embodiment of the disclosed method comprises input latches and buffers 44, address decode logic 46 to determine the selected blocks, mode select logic 48 to determine the requested operation, delay circuitry 50 to minimize current loading, and level shifters 52 to convert logic signals to voltage levels appropriate to control the output drive circuitry 54.