Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Abstract: In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Abstract: In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

Abstract: This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.

Abstract: A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.