Patents by Inventor Kevin L. Daberkow
Kevin L. Daberkow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10664421Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.Type: GrantFiled: May 24, 2019Date of Patent: May 26, 2020Assignee: FACEBOOK TECHNOLOGIESInventors: Jeremy Chan, Drew E. Wingard, Chien-Chun Chou, Hervé Jacques Alexanian, Kevin L. Daberkow, Harutyun Aslanyan, Timothy A. Pontius
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Patent number: 10303628Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.Type: GrantFiled: December 21, 2015Date of Patent: May 28, 2019Assignee: Sonics, Inc.Inventors: Jeremy Chan, Drew E. Wingard, Chien-Chun Chou, Hervé Jacques Alexanian, Kevin L. Daberkow, Harutyun Aslanyan, Timothy A. Pontius
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Publication number: 20160188501Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.Type: ApplicationFiled: December 21, 2015Publication date: June 30, 2016Inventors: Jeremy Chan, Drew E. Wingard, Chien-Chun Chou, Hervé Jacques Alexanian, Kevin L. Daberkow, Harutyun Aslanyan, Timothy A. Pontius
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Patent number: 6341324Abstract: A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.Type: GrantFiled: October 6, 1995Date of Patent: January 22, 2002Assignee: LSI Logic CorporationInventors: Robert L. Caulk, Jr., Hidetaka Magoshi, Kevin L. Daberkow
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Patent number: 5016167Abstract: In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste pipe flows making requests to the busy interleaves. The predicted busy term is lowered before access to the interleaves is complete, to allow for the latency between the time the processor sets up the request and the time the main store system receives it. Contention occurs when several processors request access to the same interleave of main store. To detect deadlocks, a counter for each processor keeps track of the number of consecutive requests from that processor which have been rejected. Once the number reaches a threshold for a first processor, its counter initiates a state machine which inhibits other processors from making requests to the main store until the first processor is successful in gaining access.Type: GrantFiled: December 21, 1987Date of Patent: May 14, 1991Assignee: Amdahl CorporationInventors: Kham X. Nguyen, Theodore S. Robinson, Michael D. Taylor, Kevin L. Daberkow
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Patent number: 4872111Abstract: In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.Type: GrantFiled: August 18, 1988Date of Patent: October 3, 1989Assignee: Amdahl CorporationInventors: Kevin L. Daberkow, Christopher D. Finan, Joseph A. Petolino, Daniel Carl Sobottka, Jeffrey A. Thomas
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Patent number: 4855904Abstract: In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.Type: GrantFiled: September 22, 1988Date of Patent: August 8, 1989Assignee: Amdahl CorporationInventors: Kevin L. Daberkow, Christopher D. Finan, Joseph A. Petolino, Daniel C. Sobottka, Jeffrey A. Thomas