Patents by Inventor Kevin L Denis
Kevin L Denis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11168188Abstract: The process to fabricate a polymer film includes baking a cyclic olefin copolymer (COC) and a silicon wafer at a predefined temperature. The process also includes attaching a plastic tape frame to the silicon wafer and submerging the COC and the plastic tape frame within water allowing one or more ultra-thin sheets of COC film to be peeled off.Type: GrantFiled: March 14, 2019Date of Patent: November 9, 2021Assignee: United States of America as represented by the Administrator of NASAInventors: Kevin L. Denis, Edward J. Wollack
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Patent number: 11101158Abstract: The disclosed subject matter relates to techniques, laminates and devices used to fabricate thin dielectric or semiconductor membranes including a handling substrate including a photoresist material on a first surface thereof, a semiconductor wafer having a circuit pattern on a first surface and a second surface to be processed and a temporary adhesive layer temporarily bonding the first surface of the semiconductor wafer to the first surface of the handling substrate including the photoresist material.Type: GrantFiled: August 8, 2018Date of Patent: August 24, 2021Assignee: United States of America as represented by the Administrator of NASAInventors: Ari D. Brown, Joseph Oxborrow, Vilem Mikula, Kevin L. Denis, Timothy M. Miller
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Patent number: 11007685Abstract: Processes for fabricating structured, relatively large area, ultra-thin polymer films are disclosed. For instance, such a process may include spinning a thermoplastic polymer film onto an etched wafer that serves as a mold for the thermoplastic polymer film, baking the thermoplastic polymer film on a hotplate at a curing temperature, delaminating the thermoplastic polymer film in water, and peeling the thermoplastic polymer film from the etched wafer, producing a structured thermoplastic polymer film that has structures corresponding to areas where the wafer has been etched.Type: GrantFiled: September 26, 2018Date of Patent: May 18, 2021Assignee: United States of America as represented by the Administrator of NASAInventors: Kevin L. Denis, Edward J. Wollack, Adrian N. Daw, Douglas M. Rabin
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Patent number: 10663350Abstract: A phononic filter includes a metamaterial body including a membrane including a crystalline or amorphous dielectric material, an elemental superconductor or an alloyed superconductor; and a plurality of spaced features. The spaced features includes holes, spacings, or apertures in the metamaterial body.Type: GrantFiled: June 22, 2018Date of Patent: May 26, 2020Assignee: United States of America as represented by the Administration of NASAInventors: Edward J. Wollack, David T. Chuss, Kevin L. Denis, Samuel H. Moseley, Karwan Rostem
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Patent number: 10074764Abstract: A method of forming low-energy x-ray absorbers. Sensors may be formed on a semiconductor, e.g., silicon, wafer. A seed metal layer, e.g., gold, is deposited on the wafer and patterned into stem pads for electroplating. Stems, e.g., gold, are electroplated from the stem seed pads through a stem mask. An absorber layer, e.g., gold, is deposited on the wafer, preferably e-beam evaporated. After patterning the absorbers, absorber and stem mask material is removed, e.g., in a solvent bath and critical point drying.Type: GrantFiled: September 29, 2016Date of Patent: September 11, 2018Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Thomas R. Stevenson, Manuel A. Balvin, Kevin L. Denis, John E. Sadleir, Peter C. Nagler
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Publication number: 20180090662Abstract: A method of forming low-energy x-ray absorbers. Sensors may be formed on a semiconductor, e.g., silicon, wafer. A seed metal layer, e.g., gold, is deposited on the wafer and patterned into stem pads for electroplating. Stems, e.g., gold, are electroplated from the stem seed pads through a stem mask. An absorber layer, e.g., gold, is deposited on the wafer, preferably e-beam evaporated. After patterning the absorbers, absorber and stem mask material is removed, e.g., in a solvent bath and critical point drying.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Inventors: THOMAS R. STEVENSON, MANUEL A. BALVIN, KEVIN L. DENIS, JOHN E. SADLEIR, PETER C. NAGLER
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Patent number: 9865795Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.Type: GrantFiled: September 30, 2016Date of Patent: January 9, 2018Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Kevin L. Denis
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Patent number: 8389381Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: June 29, 2010Date of Patent: March 5, 2013Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 8077141Abstract: A backplane for an electro-optic display comprises a pixel electrode (104), a voltage supply line (C) arranged to supply a voltage to the pixel electrode (104), and a micromechanical switch (106, 112) disposed between the voltage supply line (C) and the pixel electrode (104), the micromechanical switch (106, 112) having an open state, in which the voltage supply line (C) is not electrically connected to the pixel electrode (104), and a closed state, in which the voltage supply line (C) is electrically connected to the pixel electrode (104).Type: GrantFiled: March 12, 2008Date of Patent: December 13, 2011Assignee: E Ink CorporationInventors: Gregg M. Duthaler, Robert W. Zehner, Charles Howie Honeyman, Kevin L. Denis, Matthew A. King, Jianna Wang
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Publication number: 20100265239Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7785988Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: October 1, 2008Date of Patent: August 31, 2010Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7605799Abstract: A thin-film transistor includes a gate electrode having first and second gate electrode edges on opposed sides, and a drain electrode having a first edge that overlaps the first gate electrode edge, and a second edge that overlaps the second gate electrode edge. A diode array is fabricated by successive deposition of a conductive layer, a doped semiconductor layer and an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts using a source line and a balance line.Type: GrantFiled: July 31, 2006Date of Patent: October 20, 2009Assignee: E Ink CorporationInventors: Karl R. Amundson, Yu Chen, Kevin L. Denis, Paul S. Drzaic, Peter T. Kazlas, Andrew P. Ritenour
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Publication number: 20090029527Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: October 1, 2008Publication date: January 29, 2009Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7442587Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: June 15, 2006Date of Patent: October 28, 2008Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Publication number: 20080165122Abstract: A backplane for an electro-optic display comprises a pixel electrode (104), a voltage supply line (C) arranged to supply a voltage to the pixel electrode (104), and a micromechanical switch (106, 112) disposed between the voltage supply line (C) and the pixel electrode (104), the micromechanical switch (106, 112) having an open state, in which the voltage supply line (C) is not electrically connected to the pixel electrode (104), and a closed state, in which the voltage supply line (C) is electrically connected to the pixel electrode (104).Type: ApplicationFiled: March 12, 2008Publication date: July 10, 2008Applicant: E Ink CorporationInventors: Gregg M. Duthaler, Robert W. Zehner, Charles H. Honeyman, Kevin L. Denis, Matthew A. King, Jianna Wang
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Patent number: 7365733Abstract: A backplane for an electro-optic display comprises a pixel electrode (104), a voltage supply line (C) arranged to supply a voltage to the pixel electrode (104), and a micromechanical switch (106, 112) disposed between the voltage supply line (C) and the pixel electrode (104), the micromechanical switch (106, 112) having an open state, in which the voltage supply line (C) is not electrically connected to the pixel electrode (104), and a closed state, in which the voltage supply line (C) is electrically connected to the pixel electrode (104).Type: GrantFiled: December 16, 2003Date of Patent: April 29, 2008Assignee: E Ink CorporationInventors: Gregg M. Duthaler, Robert W. Zehner, Charles H. Honeyman, Kevin L. Denis, Matthew A. King, Jianna Wang
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Patent number: 7365394Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.Type: GrantFiled: August 17, 2004Date of Patent: April 29, 2008Assignee: E Ink CorporationInventors: Kevin L Denis, Yu Chen, Paul S Drzaic, Joseph M Jacobson, Peter T Kazlas
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Patent number: 7116318Abstract: A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.Type: GrantFiled: April 24, 2003Date of Patent: October 3, 2006Assignee: E Ink CorporationInventors: Karl R. Amundson, Yu Chen, Kevin L. Denis, Paul S. Drzaic, Peter T. Kazlas, Andrew P. Ritenour
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Patent number: 6973838Abstract: A non-contacting sensor based on inductive coupling for detecting failure initiation, and crack propagation in composite materials is disclosed. A very low cost crack sensing transducer or test pattern that can be imbedded into a structural material, interrogated, and powered wirelessly is described. A detection method for interrogating the crack sensor utilizing RF inductive coupling is disclosed. The proposed sensor consists of minimal components resulting in maximum reliability.Type: GrantFiled: April 12, 2004Date of Patent: December 13, 2005Assignee: XenotranCorp.Inventor: Kevin L Denis
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Patent number: 6825068Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.Type: GrantFiled: April 17, 2001Date of Patent: November 30, 2004Assignee: E Ink CorporationInventors: Kevin L. Denis, Yu Chen, Paul S. Drzaic, Joseph M. Jacobson, Peter T. Kazlas