Abstract: Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error correcting information are stored in a random access memory within a solid state drive.

Abstract: Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error correcting information are stored in a random access memory within a solid state drive.

Abstract: Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip.

Abstract: Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays.

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop bus. The multi-drop bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A device to be detachably attached to a mechanical substructure includes rails on opposed sides joined at the front by a cross member. A pair of guides mounted on the substructure slidably receives and retains the rails upon attachment of the device. An alignment pin extending from a rail mates with a hole in one of the guides to insure alignment of an electrical connector of the device with an electrical connector mounted on the substructure. The cross member includes screws for securing the cross member to the substructure. A spring extending from a rail makes electrical contact with an adjacent guide and an electrostatic discharge contact plate to discharge any existing static charge.

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays.