Abstract: A method and apparatus for allocation of shared spectrum in a wireless communication system uses a radio frequency (RF) beacon signal that is transmitted between access points of the wireless communication system. The information content of the RF beacon signal includes an identifier of the access point that generated the signal, identifiers of clients of that access point; and identifiers of the communication channels assigned to those clients. The client identifier may include at least part of an Internet Protocol (IP) address of the client. Additionally the beacon signal may contain client attributes to enable negotiation of the sharing of available communication channels between access points and clients.

Abstract: A method and apparatus for efficient management of hierarchically administered spectrum resources in a communications network are disclosed.

Abstract: A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate control of a shared bus (38). A processor indicates that it is the master (20) by setting the start bit (120). It enters an arbitration by setting the request bit (124). The set of priority bits (134) contains a binary priority value encoded in bit major order. This format allows an optimized parallel comparison (128, 130) of the priority values for each of the requesting processors a bit at a time. Finally, processors drop out of the arbitration upon detecting (136) a parity error in an arbitration token received from another processor.

Abstract: A serial arbitration system for arbitration between multiple processors (20, 21, 22) in a low power system has an arbitration line driven by each of the processors and received by each of the other processors. The arbitration lines (30, 31, 32) are coupled to arbitration ports (60, 61, 62, 63, 64) on each processor (20, 21, 22) numbered from zero for the driven arbitration port (60). Each of the processors (20, 21, 22) has a processor ID number, with a master processor (20) having ID zero. The arbitration line (30) driven by the master processor (20) is coupled to each other processor (21, 22) on the arbitration port (61', 62') numbered equal to the processor ID of that other processor (21, 22). The driven arbitration lines (31, 32) from the other processors (21, 22) are coupled to the arbitration ports (61, 62) on the master processor (20) corresponding to the processor ID of the driving processor (21, 22).

Abstract: A transceiver (20) communicates audio and non-audio data between a variety of digital audio sources and sinks. Transceiver (20) has a receiver (34, 38) which communicates data between a modulated digital audio source (12) and an unmodulated digital audio sink (28), and a transmitter (42, 46) which communicates data between an unmodulated digital audio source (22) and a modulated digital audio sink (16). Digital data is transferred from receiver (34, 38) or received in transmitter (42, 46) in one of a plurality of eight formats. Each of the formats is designed to enable transceiver (20) to interface with a variety of digital audio sinks and sources without additional circuitry. A plurality of mode control pins determine the format provided to transceiver (20) when transmitting or receiving digital audio data.

Abstract: A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.

Abstract: A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.

Abstract: An interface transceiver (16) circuit and method for communicating transceiver control and status information between a signal processor (20) and either an audio source (12) or an audio sink (24). During transmission of digital audio data from audio source (12) and signal processor (20), a comparator (49) compares a cyclic redundancy check (CRCC) byte of a block of channel status information to a theoretical CRCC byte generated by a CRC generator (48). By comparing actual and theoretical CRCC bytes, comparator (49) indicates in a single bit whether audio data was transmitted correctly. Remaining bits of the CRCC byte are then used to transfer status information corresponding to transceiver (16). Similarly, during transmission of digital data from signal processor (20) to audio sink (24), a parity bit of a subframe of the digital data is used to transfer programming information from signal processor (20) to audio sink (24).

Abstract: An interface circuit (16, 44) is provided for communicating a plurality of demodulated digital audio values in a predetermined serial data bus protocol between a digital source (12) and a digital sink (46). Each of the plurality of digital audio values contains either left or right channel audio information and control values. The serial data bus protocol is formed by the interface circuit (16, 44) by transmitting a left channel information value of a predetermined demodulated digital audio value, a right channel information value of the predetermined demodulated digital audio value, and then a byte of control information formed from both the left and right channel control values.

Abstract: A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

Abstract: A modulo arithmetic unit for providing a sum or difference of two numbers of arbitrary value in a selected one of a plurality of moduli is provided. Each modulus has a lower and an upper boundary and a range of intermediate values. First and second adders are provided for respectively providing first and second outputs which respectively represent outputs compensated for and not compensated for a possible wraparound of the upper or lower boundary. Control circuitry is used to detect whether a wraparound occurred during the calculation depending upon the value of selective interstage carry signals of the first and second adders. The correct output is provided as a selected one of the outputs of the first and second adders in response to the control circuitry.

Abstract: A stereo decoder is provided for decoding an encoded stereo signal. In one form, the encoded stereo signal is digitized and coupled to two sampling circuits. By selectively sampling the encoded signal relative to a stereo pilot signal contained in the encoded signal, both a left-hand audio signal and a right-hand audio signal may be separately recovered from the encoded signal and latched. A phase locked loop monitors the phase of the stereo pilot signal relative to the encoded signal and controls the time sampling of the encoded signal at predetermined phases of the pilot signal. The stereo decoding may also be performed by using analog circuitry to directly time sample the encoded stereo signal. In an analog approach, the time sampled output signal must be low pass filtered to provide decoded stereo output signals.

Abstract: A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.

Abstract: A data processor control unit which provides instructions for execution by a data processor and minimizes instruction cycles lost as overhead. A pipelined instruction stream is used in which instruction addresses are selectively coupled from a program counter and a prefetch counter to a program memory which provides actual instructions. The instructions are stored in a prefetched register, decoded and then loaded into an instruction register coupled to the data processor. When an interrupt service request is made by a device peripheral to the processor, the prefetch instruction address flow is immediately redirected and a predetermined number of interrupt instruction words are prefetched by an interrupt address generator before completion of execution of normal program instructions has occurred. Therefore, interrupt instructions are fetched and jammed into a pipelined instruction stream regardless of instruction cycle boundaries.

Abstract: A data processing system having apparatus for selectively executing nested do loops with minimum overhead is provided. The apparatus may be added to a system which executes do loops. The method of execution of the do loops may be any of a myriad of conventional methods. Memory storage is provided for storing the number of iterations remaining in a do loop and an active loop flag. The active loop flag indicates that a do loop is active and enables the do loop apparatus. The active loop flag also indicates whether the data stored in memory is associated with an active loop. New parameters relating to the nested do loop may be used by the same circuitry which executes the do loop thereby eliminating duplication of circuitry. Upon termination of the nested do loop, the memory storage restores the information required to complete the do loop by the apparatus.

Abstract: An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.

Abstract: A digital communication system including an encoder and decoder for the transmission of digital information over a transmission medium, the system having automatic frame synchronization and error correction requiring a minimum of tansmission bits and decoding time. The encoder processes a data stream and generates a transmission bit stream of N bits using convolutional encoding, autosynchronization sequence combining, and bit interleaving. The multi-phase sequential decoder decodes the received coded data, corrects transmission errors and automatically achieves frame synchronization from P selected phases of the received data. This is accomplished by selecting the phase of the received data with the best metric, bit de-interleaving, removing the autosynchronization sequence and comparing the received data of the selected phase with the extended code word subsets from the node having the best metric.

Abstract: A soft quantizer for assigning numerical weights to hard quantized output bits of a binary digital detector in a digital receiver based on the noise energy level of the received baseband data. An analog signal, derived from the discriminator noise level, is digitized by an analog to digital converter for use as an address to look up predetermined numerical weights for soft quantized values in a memory table. The addressed numerical weights are combined with the hard quantized output bits of the digital detector to generate soft quantized data values.