Abstract: A low capacitance, high performance semiconductor device is described having a sidewall emitter wherein the emitter width is relatively small (approximately 0.5 micrometers). This enables a small emitter-base interface which reduces capacitance. Additionally, the regions of the base and collector near their interface are lightly doped so that collector-base capacitance is greatly reduced.

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar.The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown.

Abstract: A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.

Abstract: A BIMOS memory cell is formed by providing a CMOS static RAM cell with an additional NPN bipolar transistor to provide additional drive current during the read cycle to improve the read time of the memory cell.

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown.

Abstract: Base-collector capacitance is reduced in a semiconductor device by making use of a buried oxide that is self-aligned to an active region of the semiconductor device. Use of the buried oxide provides a means for down-scaling or shrinking of the active device region which in turn increases the speed of the device. In addition, the area above the buried oxide is built up to reduce the resistance in the active region.

Abstract: A BICMOS three state gate is provided having high noise immunity, low power requirements, high drive capability, and good output signal switching characteristics. A first bipolar transistor has its collector-emitter path coupled between a first voltage terminal and an output terminal. A second bipolar transistor has its collector-emitter path coupled between the output terminal and a second voltage terminal. A first MOS circuit is coupled between first and second voltage terminals and to the first input terminal and a base of the first bipolar transistor for biasing the first bipolar transistor. A second MOS circuit is coupled between the base of the first bipolar transistor and the second voltage terminal and to the first input terminal and a base of the second bipolar transistor for biasing the second bipolar transistor. A third MOS circuit is coupled between a second input terminal and both of the first and second MOS circuits for disabling the first and second bipolar transistors.

Abstract: A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer.The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between an upper NPN and a lower PNP pair of push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A P-channel MOS transistor is coupled between a node and both the collector of the NPN transistor and a first supply voltage terminal for biasing the NPN transistor. An N-channel MOS transistor is coupled between the node and both the collector of the PNP transistor and a second supply voltage terminal for biasing the PNP transistor. The gates of the MOS devices are connected to an input terminal. The node is further coupled to the bases of the NPN and PNP transistors and is coupled to the output terminal by a transmission gate or a resistor for increasing the output voltage swing.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled between an input terminal and the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between the input terminal and the upper transistor for biasing the upper transistor. A circuit device is coupled between the output terminal and the upper transistor for increasing the output voltage swing.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled between an input terminal and the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between the input terminal and the upper transistor for biasing the upper transistor. A third circuit is coupled between the input terminal and the lower transistor and is responsive to the output terminal for biasing the lower transistor.

Abstract: A BIMOS memory sense amplifier is provided having the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A pair of differentially connected NPN transistors are coupled for receiving a first and a second bit current from the bit lines of a memory circuit. A MOS transistor circuit is coupled to the NPN transistors and is responsive to a differential output therefrom, for buffering two NPN push-pull output transistors.