Patents by Inventor Kevin LAI LIN

Kevin LAI LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043565
    Abstract: Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Kevin Lai Lin, Miriam Ruth Reshotko, Nafees Aminul Kabir
  • Publication number: 20210043500
    Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Kevin Lai LIN, Mauro KOBRINSKY, Mark ANDERS, Himanshu KAUL, Ram KRISHNAMURTHY
  • Publication number: 20210043567
    Abstract: Embodiments disclosed herein include a semiconductor device with interconnects with non-uniform heights. In an embodiment, the semiconductor device comprises a semiconductor substrate, and a back end of line (BEOL) stack over the semiconductor substrate. In an embodiment, the BEOL stack comprises first interconnects and second interconnects in an interconnect layer of the BEOL stack. In an embodiment, the first interconnects have a first height and the second interconnects have a second height that is different than the first height.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Mark ANDERS, Himanshu KAUL, Ram KRISHNAMURTHY, Kevin Lai LIN, Mauro KOBRINSKY
  • Publication number: 20200411427
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Kevin Lai LIN, Manish CHANDHOK, Miriam RESHOTKO, Christopher JEZEWSKI, Eungnak HAN, Gurpreet SINGH, Sarah ATANASOV, Ian A. YOUNG
  • Patent number: 10457548
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lai Lin, Chytra Pawashe, Raseong Kim, Ian A. Young, Kanwal Jit Singh, Robert L. Bristol
  • Publication number: 20180086627
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 29, 2018
    Inventors: Kevin LAI LIN, Chytra PAWASHE, Raseong KIM, Ian A. YOUNG, Kanwal Jit SINGH, Robert L. BRISTOL