Patents by Inventor Kevin Lally

Kevin Lally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7801635
    Abstract: The invention can provide a method of etch processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer data to create, modify, and/or use etch recipe data, etch profile data, and/or etch model data. In addition, RTPT procedures can use real-time wafer data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: September 21, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Patent number: 7642102
    Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer thickness data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer thickness data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: January 5, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Patent number: 7623978
    Abstract: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites on the wafer. For each measurement site in the first set of measurement sites, the optical metrology process determines an amount of damage of a damaged area of a periodic grating in the measurement site. The damage-assessment data includes the amount of damage determined by the optical metrology process. A first damage-assessment map is created for the dual damascene process. The first damage-assessment includes the damage-assessment data and the locations of the first set of measurement sites on the wafer. One or more values in the damage-assessment map are compared to damage-assessment limits established for the dual damascene process to identify the wafer as a damaged or undamaged wafer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 24, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Patent number: 7619731
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology includes directing an incident beam on the damaged structure. A diffracted beam is received from the damaged structure. The received diffracted beam is processed to determine a profile of an undamaged portion of the damaged structure and to measure an amount of dielectric damage of the damaged structure.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 17, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Patent number: 7576851
    Abstract: A method of creating a library for measuring a plurality of damaged structures formed on a semiconductor wafer using optical metrology includes directing an incident beam on a first damaged structure. The first damaged structure was formed by modifying at least one process parameter in a dual damascene procedure. A diffracted beam is received from the first damaged structure. A measured diffraction signal is obtained based on the received diffracted beam. A first simulated diffraction signal is calculated. The first simulated diffraction signal corresponds to a hypothetical profile of the first damaged structure. The hypothetical profile includes an undamaged dielectric portion and a damaged dielectric portion. The measured diffraction signal is compared to the first simulated diffraction signal.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: August 18, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Patent number: 7571074
    Abstract: A method for facilitating an ODP (optical digital profile) measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on the wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying. The real time wafer characteristic data may be real time wafer thickness data.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: August 4, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Patent number: 7477960
    Abstract: A method for implementing FDC in an APC system including receiving an FDC model from memory; providing the FDC model to a process model calculation engine; computing a vector of predicted dependent process parameters using the process model calculation engine; receiving a process recipe comprising a set of recipe parameters, providing the process recipe to a process module; executing the process recipe to produce a vector of measured dependent process parameters; calculating a difference between the vector of predicted dependent process parameters and the vector of measured dependent process parameters; comparing the difference to a threshold value; and declaring a fault condition when the difference is greater than the threshold value.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: January 13, 2009
    Assignee: Tokyo Electron Limited
    Inventors: James E. Willis, Merritt Funk, Kevin Lally, Kevin Pinto, Masayuki Tomoyasu, Raymond Peterson, Radha Sundararajan
  • Publication number: 20080183312
    Abstract: The invention can provide a method of etch processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer data to create, modify, and/or use etch recipe data, etch profile data, and/or etch model data. In addition, RTPT procedures can use real-time wafer data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080183412
    Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer thickness data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer thickness data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080183411
    Abstract: A method for facilitating an ODP measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on said wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying. The real time wafer characteristic data may be real time wafer thickness data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080137078
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Application
    Filed: January 28, 2008
    Publication date: June 12, 2008
    Applicant: Tokyo Electron Limited
    Inventors: Kevin LALLY, Merritt FUNK, Radha SUNDARARAJAN
  • Publication number: 20080027577
    Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.
    Type: Application
    Filed: October 2, 2007
    Publication date: January 31, 2008
    Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager
  • Patent number: 7324193
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Publication number: 20070232045
    Abstract: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites on the wafer. For each measurement site in the first set of measurement sites, the optical metrology process determines an amount of damage of a damaged area of a periodic grating in the measurement site. The damage-assessment data includes the amount of damage determined by the optical metrology process. A first damage-assessment map is created for the dual damascene process. The first damage-assessment includes the damage-assessment data and the locations of the first set of measurement sites on the wafer. One or more values in the damage-assessment map are compared to damage-assessment limits established for the dual damascene process to identify the wafer as a damaged or undamaged wafer.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Publication number: 20070229806
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology includes directing an incident beam on the damaged structure. A diffracted beam is received from the damaged structure. The received diffracted beam is processed to determine a profile of an undamaged portion of the damaged structure and to measure an amount of dielectric damage of the damaged structure.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Publication number: 20070229807
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Publication number: 20070233404
    Abstract: A method of creating a library for measuring a plurality of damaged structures formed on a semiconductor wafer using optical metrology includes directing an incident beam on a first damaged structure. The first damaged structure was formed by modifying at least one process parameter in a dual damascene procedure. A diffracted beam is received from the first damaged structure. A measured diffraction signal is obtained based on the received diffracted beam. A first simulated diffraction signal is calculated. The first simulated diffraction signal corresponds to a hypothetical profile of the first damaged structure. The hypothetical profile includes an undamaged dielectric portion and a damaged dielectric portion. The measured diffraction signal is compared to the first simulated diffraction signal.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Publication number: 20060184264
    Abstract: A method for implementing FDC in an APC system including receiving an FDC model from memory; providing the FDC model to a process model calculation engine; computing a vector of predicted dependent process parameters using the process model calculation engine; receiving a process recipe comprising a set of recipe parameters, providing the process recipe to a process module; executing the process recipe to produce a vector of measured dependent process parameters; calculating a difference between the vector of predicted dependent process parameters and the vector of measured dependent process parameters; comparing the difference to a threshold value; and declaring a fault condition when the difference is greater than the threshold value.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 17, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: James Willis, Merritt Funk, Kevin Lally, Kevin Pinto, Masayuki Tomoyasu, Raymond Peterson, Radha Sundararajan
  • Publication number: 20060007453
    Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.
    Type: Application
    Filed: July 12, 2004
    Publication date: January 12, 2006
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOKYO ELECTRON LIMITED
    Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager