Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: An integrated steering gear, frame structure and engine mount base for a vehicle includes an elongate, generally hollow housing having at least one mounting portion at each of opposing ends. A steering gear including a steering gear input and a pair of opposingly-oriented tie rods is assembled within the hollow housing such that the steering gear input and the tie rods extend from the interior of the housing. An engine mount base is integrated into the housing. The integrated steering gear, frame structure and engine mount base is mountable to a vehicle support frame to function as a subframe member of the support frame.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: An integrated steering gear, frame structure and engine mount base for a vehicle includes an elongate, generally hollow housing having at least one mounting portion at each of opposing ends. A steering gear including a steering gear input and a pair of opposingly-oriented tie rods is assembled within the hollow housing such that the steering gear input and the tie rods extend from the interior of the housing. An engine mount base is integrated into the housing. The integrated steering gear, frame structure and engine mount base is mountable to a vehicle support frame to function as a subframe member of the support frame.

Abstract: Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.