Abstract: A method for power plane splitting. The method enables the traces on a power plane to be organized so that the conductor area is expanded while still ensuring that components with similar power supply requirements are coupled to the same trace. A potential field of a power plane of a printed circuit board is calculated by assigning one or more potential values to one or more components coupled to the printed circuit board and solving for a plurality of potential field values at a plurality of locations between the one or more components. One or more boundaries between the one or more components are defined by selecting contours of constant potential within the calculated potential field. One or more traces on the power plane are created using the one or more boundaries, wherein the one or more traces connect a corresponding one or more pluralities of components and each plurality of components of the one or more.

Abstract: A method for power plane splitting. The method enables the traces on a power plane to be organized so that the conductor area is expanded while still ensuring that components with similar power supply requirements are coupled to the same trace. A potential field of a power plane of a printed circuit board is calculated by assigning one or more potential values to one or more components coupled to the printed circuit board and solving for a plurality of potential field values at a plurality of locations between the one or more components. One or more boundaries between the one or more components are defined by selecting contours of constant potential within the calculated potential field. One or more traces on the power plane are created using the one or more boundaries, wherein the one or more traces connect a corresponding one or more pluralities of components and each plurality of components of the one or more.

Abstract: A data accelerator for use in a test vector sequencer includes a data translator, a plurality of sequence memory devices, and a switch. The data translator and the switch are configured via a control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to transfer a previously stored data segment. The test sequencer forwards a first application segment to a first memory device and acquires a subsequent application with a second memory device, detects a condition responsive to the completion of the segment acquisition and forwarding tasks, switches the roles of the first and second memory devices, and repeatedly switches and detects until all application segments have been processed.

Abstract: An improved system and method for increasing system throughput and data capacity in a circuit tester capable of programming and/or testing in-circuit integrated circuit devices are disclosed. A data accelerator for use in a test vector sequencer can be realized with a data translator, a plurality of sequence memory devices, and a switch. In preferred embodiments, the data translator and the switch are configured via a single control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to transfer a previously stored data segment.