Patents by Inventor Kevin Lite

Kevin Lite has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER
    Publication number: 20090215202
    Abstract: An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 27, 2009
    Applicant: Siltronic Corporation
    Inventors: Kevin Lite, Quynh Tran
  • CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER
    Publication number: 20090214843
    Abstract: An epitaxial silicon wafer is provided with a thickness in the area adjacent the edge that is greater or less than the thickness adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge thickness.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 27, 2009
    Applicant: Siltronic Corporation
    Inventors: Kevin Lite, Quynh Tran
  • System and method for characterizing silicon wafers
    Patent number: 7474114
    Abstract: A method and system is provided for characterizing silicon wafers. The method and system provide for measuring a resistance between a pair of points on an epitaxial layer of a wafer's surface. The points may be substantially equidistant from the center of the wafer. The resistance measuring may be repeated at a series of pairs of points, each pair of points being radially spaced apart from an adjacent pair of points. The series of pairs of points may include a control group of pairs. A figure of merit may be calculated by subtracting from 1.0 the ratio of a minimum resistance of the resistances measured between the pairs of points to an average of the resistances measured between the pairs of points in the control.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: January 6, 2009
    Assignee: Sitronic Corporation
    Inventor: Kevin Lite
  • System and method for characterizing silicon wafers
    Publication number: 20070069760
    Abstract: A method and system is provided for characterizing silicon wafers. The method and system provide for measuring a resistance between a pair of points on an epitaxial layer of a wafer's surface. The points may be substantially equidistant from the center of the wafer. The resistance measuring may be repeated at a series of pairs of points, each pair of points being radially spaced apart from an adjacent pair of points. The series of pairs of points may include a control group of pairs. A figure of merit may be calculated by subtracting from 1.0 the ratio of a minimum resistance of the resistances measured between the pairs of points to an average of the resistances measured between the pairs of points in the control.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 29, 2007
    Inventor: Kevin Lite