Patents by Inventor Kevin Locker
Kevin Locker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10747633Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.Type: GrantFiled: September 24, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Kevin Locker, Sai Ram Dheeraj Lokam, Siva Prasad Kota, Massimo Ceppi, Teo Cupaiuolo
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Publication number: 20190050514Abstract: A method to perform a hybrid Register Transfer Level (RTL)/gate-level (GL) fault injection simulation of a hardware design comprises generating a list of one or more fault nodes in a GL netlist for the hardware design, mapping functionally equivalent comparison points between RTL logic for the hardware design and GL netlist of the hardware design, identifying a nearest set of downstream comparison points for one or more logic paths for the one or more fault nodes, identifying a nearest set of upstream comparison points for the one or more identified downstream comparison points, replacing RTL logic with equivalent GL netlist logic to provide hybrid RTL/GL netlist in code, and performing fault injection simulating using the hybrid RTL/GL netlist codeType: ApplicationFiled: June 28, 2018Publication date: February 14, 2019Applicant: Intel CorporationInventors: Massimo Ceppi, Teo Cupaiuolo, Mauro Pipponzi, Kevin Locker
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Publication number: 20190050307Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.Type: ApplicationFiled: September 24, 2018Publication date: February 14, 2019Inventors: Kevin Locker, Sai Ram Dheeraj Lokam, Siva Prasad Kota, Massimo Ceppi, Teo Cupaiuolo
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Patent number: 8174327Abstract: Example embodiments are directed toward configuration of a phase lock loop (PLL) circuits for low power operation. In particular embodiments, a fraction related to a desired gain of a PLL circuit is determined. A set of possible frequency-divider values and a set of possible feedback divider values are determined. A PLL configuration is selected from a combination of the sets of frequency divider and feedback divider values that forms a ratio indicated the determined fraction.Type: GrantFiled: April 12, 2007Date of Patent: May 8, 2012Assignee: NXP B.V.Inventor: Kevin Locker
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Patent number: 7917680Abstract: A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.Type: GrantFiled: November 18, 2005Date of Patent: March 29, 2011Assignee: NXP B.V.Inventor: Kevin Locker
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Publication number: 20090261910Abstract: A phase-locked loop (PLL) circuit configuration is implemented using a variety of methods and devices. According to one example embodiment, a low power configuration is determined for the PLL circuit which meets a set of desired phase-locked loop circuit characteristics. The PLL circuit (110) has a first frequency-divider (112, 119), a feedback-divider (118) and a fractional-N mode (111).Type: ApplicationFiled: April 12, 2007Publication date: October 22, 2009Applicant: NXP B.V.Inventor: Kevin Locker
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Patent number: 7606983Abstract: A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, a controller, and at least two processors that generate requests to access the memory data. Each access request includes an indication of whether or not this request is to be performed in a sequential order among other access requests and, if so, an indication of the order. The controller receives the access requests from each processor, determines a performance order for the requests, and provides the access requests to the memory in the performance order. The performance order conforms to the specified order when the access requests so indicate.Type: GrantFiled: June 21, 2004Date of Patent: October 20, 2009Assignee: NXP B.V.Inventor: Kevin Locker
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Publication number: 20090144478Abstract: A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.Type: ApplicationFiled: November 18, 2005Publication date: June 4, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventor: Kevin Locker
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Patent number: 7376286Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.Type: GrantFiled: September 18, 2002Date of Patent: May 20, 2008Assignee: NXP B.V.Inventors: Kevin Locker, Judson Lehman
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Publication number: 20060047773Abstract: A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, a controller, and at least two processors that generate requests to access the memory data. Each access request includes an indication of whether or not this request is to be performed in a sequential order among other access requests and, if so, an indication of the order. The controller receives the access requests from each processor, determines a performance order for the requests, and provides the access requests to the memory in the performance order. The performance order conforms to the specified order when the access requests so indicate.Type: ApplicationFiled: June 21, 2004Publication date: March 2, 2006Inventor: Kevin Locker
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Publication number: 20040052431Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.Type: ApplicationFiled: September 18, 2002Publication date: March 18, 2004Applicant: Koninklijke Philips Electronics N.V.Inventors: Kevin Locker, Judson Lehman