Abstract: Described herein is a coagulant blend for use in SAGD water treatment systems. Specifically, a blend of high charge density polyamine and low charge density poly(diallylmethyl ammonium chloride (poly-DADMAC) is used in the warm lime softening treatment process to coagulate and flocculate solids.

Abstract: A weight shifting mechanism for a bogie frame is provided. The weight shifting mechanism may include an axle support pivotally coupled to the idler axle, a pusher link pivotally coupled to the axle support and forming a first fulcrum with the bogie frame, a support member pivotally coupled to the pusher link and the axle support, and an actuator mounted on the support member and actuatably coupled to the axle support via a live lever and a connector link. The live lever may form a second fulcrum with the support member and may be pivotally coupled to the connector link. The connector link may be pivotally coupled to the axle support. The actuator may selectively pivot the live lever about the second fulcrum to pivot the axle support about the idler axle and move the bogie frame relative to the idler axle.

Abstract: Described herein is a coagulant blend for use in SAGD water treatment systems. Specifically, a blend of high charge density polyamine and low charge density poly(diallylmethyl ammonium chloride (poly-DADMAC) is used in the warm lime softening treatment process to coagulate and flocculate solids.

Abstract: A weight shifting mechanism for a bogie frame is provided. The weight shifting mechanism may include an axle support pivotally coupled to the idler axle, a pusher link pivotally coupled to the axle support and forming a first fulcrum with the bogie frame, a support member pivotally coupled to the pusher link and the axle support, and an actuator mounted on the support member and actuatably coupled to the axle support via a live lever and a connector link. The live lever may form a second fulcrum with the support member and may be pivotally coupled to the connector link. The connector link may be pivotally coupled to the axle support. The actuator may selectively pivot the live lever about the second fulcrum to pivot the axle support about the idler axle and move the bogie frame relative to the idler axle.

Abstract: Systems and methods for cleaning a membrane filtration system using cross-flow geometry.

Abstract: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.

Abstract: A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.

Abstract: Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer die manufactured from the IC layout design. Amending the one or more identified assist features.

Abstract: A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.

Abstract: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.

Abstract: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device.

Abstract: An original layout of an integrated circuit is modified using optical proximity correction (OPC) to obtain a second layout. During OPC, a sensitivity to flare for each feature is conveniently identified. To map the flare, the amplitude of intensity is mapped over a field of exposure, which is typically a rectangle-shaped area corresponding to an exposure of a stepper. The field of exposure is divided into regions in which a region is characterized as having substantially the same amplitude throughout. For each feature a decision is made whether to make a further correction or not. If correction is desired, the amount of correction is based in part on the region in which the feature is located and the sensitivity of the feature. This same approach is applicable to other properties than flare that vary based on the location within the field of exposure.

Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Abstract: A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.

Abstract: A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Abstract: In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.

Abstract: A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Abstract: Lithographic Proximity Correction (LPC) shapes are added (503) to a layer of a layout database file (501). Geometric criteria such as feature width are then used to filter the added LPC shapes (502). The LPC shapes are then modified (505) by determining which LPC shapes are within a predetermined distance from a shape in a layer of the second data base (504). The database file, including the modified LPC shapes, is then used to manufacture a set of lithographic masks (506). The lithographic masks are then used to pattern a set of wafers in the manufacture of integrated circuits (507).

Abstract: A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.

Abstract: The present invention provides an anti-reflective Ta.sub.3 N.sub.5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta.sub.3 N.sub.5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer (16). A dielectric tantalum nitride layer (18) is deposited on top of the first dielectric layer. A second dielectric layer (20) is deposited on the tantalum nitride layer. A dual damascene opening (34) is etched into the dielectric layers by patterning a first opening portion (26) and a second opening portion (32) using photolithography operations. Dielectric tantalum nitride layer (18) serves as an ARC layer during these operations to reduce the amount of reflectance from conductive region (14) to reduce distortion of the photoresist pattern. The use of a dielectric tantalum nitride layer as an ARC is particularly suitable for I line and G line lithography.