Abstract: The present invention is directed to providing a computer system which arbitrates control of a shared bus among plural devices included in the computer system. In accordance with the present invention, at least one of the devices is afforded a higher priority than the remaining devices, yet none of the remaining devices are effectively denied system bus access or control for extended periods of time. The present invention can therefore increase operating efficiency even as the number of devices included in the computer system is increased to achieve enhanced processing power. In addition, the present invention can provide sophisticated multimedia features, including real time signal processing, without sacrificing overall operating efficiency.

Abstract: A method and system for transferring units of data between a computer memory and an external system in which a DMA controller stores and uses information from an I/O device interfacing with the external system to transfer data more efficiently.

Abstract: An apparatus for and method of controlling data transfers in which the data is in a predefined format. The DMA controller with a status register cooperates with a counter capable of effecting a change in the contents of the status register to generate predefined leading sequences of pulses. The arrangement may also include a module which can detect a predefined trailing sequence and effect a change in the contents of the status register.

Abstract: The present invention is directed to providing a computer system which arbitrates control of a shared bus among plural devices included in the computer system. In accordance with the present invention, at least one of the devices is afforded a higher priority than the remaining devices, yet none of the remaining devices are effectively denied system bus access or control for extended periods of time. The present invention can therefore increase operating efficiency even as the number of devices included in the computer system is increased to achieve enhanced processing power. In addition, the present invention can provide sophisticated multimedia features, including real time signal processing, without sacrificing overall operating efficiency.

Abstract: A DMA controller capable of conditional action under the control of a status register, prespecified parameters, and a condition field of the channel command, and a DMA controller which returns status information to command entry locations that are reserved for this purpose are disclosed. The prespecified parameters may be held in a register having a mask field and a value field, and a test for conditional action may be a masked comparison of the status register and the value field. The condition field determines how the test result is interpreted and allows suppressing or forcing the conditional action during a command.

Abstract: The present invention is therefore directed to enhancing the efficiency with which input/output controllers execute operations in response to requests from another device, such as a main controller. In accordance with exemplary embodiments, a compact set of status information signals is communicated from an input/output controller to a main controller such that the main controller can provide error control (that is, monitor input/output controller operation) without the use of interrupts. As a result, the main controller can sequentially and continuously supply multiple commands of a transaction to the input/output controller without the use of a multiple hardware interrupts. System hardware can therefore be used more efficiently and input/output controller operation can be accelerated, thereby increasing system performance.

Abstract: A method and system for transferring units of data between a computer memory and an external system in which a DMA controller stores and uses information from an I/O device interfacing with the external system to transfer data more efficiently.