Patents by Inventor Kevin M. Durocher

Kevin M. Durocher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220382766
    Abstract: Techniques for suggesting media assets, the technique including: requesting a set of candidate media assets for a set of user media items based on a knowledge graph metadata network describing the set of user media items; receiving metadata for the set of candidate media assets; determining one or more sets of ranked media assets based on the received metadata; and outputting the determined one or more sets of ranked media assets.
    Type: Application
    Filed: May 2, 2022
    Publication date: December 1, 2022
    Inventors: Nathaniel B. Chapman, Patrick H. Kelly, Eric Circlaeys, Kevin Bessiere, Brian J. Rogosky, Alfredo Ramos-Alvarez, Bruno J. Conejo, Matthias Mauch, Hao Yang, Bruno Di Giorgi, Jeremy P. Bogle, Zachary H. Smith, Betim Deva, Daniel Cartoon, Neil C. Foley, Menelaos D. Kokolios, Lewis Kaneshiro, Jorge A. Herrera Soto, James E. Hewitt, Casey W. Baker, Alexa Rockwell, Alexis H. Durocher, Trevor M. Slaton, Cristina N. Smith
  • Publication number: 20220313205
    Abstract: A deployable invasive device includes a transducer with a plurality of elements linked by at least one shape memory material configured to move the plurality of elements relative to one another between a first configuration and a second configuration in response to a stimulus. The shape memory material comprises at least one active region configured to facilitate transition between the first configuration and the second configuration. The deployable invasive device includes at least one integrated circuit configured to process signals from at least one of the plurality of elements and a plurality of conductive traces on or in the shape memory material and extending through the active region. The conductive traces are configured to conduct signals to the at least one integrated circuit, wherein the conductive traces are configured to conform as the shape memory material moves the elements between the first configuration and the second configuration.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 6, 2022
    Applicant: GE Precision Healthcare LLC
    Inventors: Edouard Da Cruz, Flavien Daloz, Kevin M. Durocher, Reinhold Brüstle, Bruno H. Haider, Giandonato Stallone
  • Publication number: 20220313206
    Abstract: A deployable invasive device includes a transducer with a plurality of elements with linked by at least one shape memory material, the at least one shape memory material configured to move the plurality of the elements relative to one another between a first configuration and a second configuration in response to the thermal stimulus. The shape memory material comprises at least one active region configured to change shape to facilitate transition between the first configuration and the second configuration. The deployable invasive device further includes at least one integral heating resistor on or within the at least one active region and configured to heat the shape memory material surrounding the integral heating resistor to provide the thermal stimulus.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 6, 2022
    Applicant: GE Precision Healthcare LLC
    Inventors: Edouard Da Cruz, Flavien Daloz, Kevin M. Durocher, Reinhold Brüstle, Bruno Haider, Giandonato Stallone
  • Patent number: 8008781
    Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: August 30, 2011
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 8008125
    Abstract: An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: August 30, 2011
    Assignee: General Electric Company
    Inventors: Paul Alan McConnelee, Kevin M. Durocher, Donald Paul Cunningham
  • Patent number: 7964974
    Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 21, 2011
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 7956457
    Abstract: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 7, 2011
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Elizabeth A. Burke, Thomas Bert Gorczyca, Charles G. Woychik
  • Publication number: 20100224992
    Abstract: An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 9, 2010
    Inventors: Paul Alan McConnelee, Kevin M. Durocher, Donald Paul Cunningham
  • Publication number: 20100132994
    Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Richard Joseph Saia, Paul A. McConnelee
  • Publication number: 20100133683
    Abstract: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Elizabeth A. Burke, Thomas Bert Gorczyca, Charles G. Woychik
  • Publication number: 20100133705
    Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 7158383
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: January 2, 2007
    Assignee: General Electric Company
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Publication number: 20040114336
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Application
    Filed: November 18, 2003
    Publication date: June 17, 2004
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Publication number: 20040063294
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Patent number: 6709944
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 23, 2004
    Assignee: General Electric Company
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Patent number: 5950303
    Abstract: A substrate stack is suspended within a stack holder to position upper and lower stack surfaces coplanar with upper and lower holder surfaces. Laminating heat and pressure is simultaneously applied to the upper and lower surfaces to laminate a carrier interconnect film to top and bottom stack portions simultaneously. Subsequent wet chemical processing of both stack edges may also be simultaneous to effect savings in manufacturing costs.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: September 14, 1999
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Paul A. McConnelee, Richard J. Saia, Kevin M. Durocher
  • Patent number: 5531018
    Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: July 2, 1996
    Assignee: General Electric Company
    Inventors: Richard J. Saia, Mario Ghezzo, Bharat S. K. Bagepalli, Kevin M. Durocher
  • Patent number: 5524339
    Abstract: In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: June 11, 1996
    Assignee: Martin Marietta Corporation
    Inventors: Bernard Gorowitz, Richard J. Saia, Kevin M. Durocher
  • Patent number: 5472539
    Abstract: A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: December 5, 1995
    Assignee: General Electric Company
    Inventors: Richard J. Saia, Kevin M. Durocher, Thomas B. Gorczyca, Mario Ghezzo