Abstract: A deployable invasive device includes a transducer with a plurality of elements with linked by at least one shape memory material, the at least one shape memory material configured to move the plurality of the elements relative to one another between a first configuration and a second configuration in response to the thermal stimulus. The shape memory material comprises at least one active region configured to change shape to facilitate transition between the first configuration and the second configuration. The deployable invasive device further includes at least one integral heating resistor on or within the at least one active region and configured to heat the shape memory material surrounding the integral heating resistor to provide the thermal stimulus.

Abstract: A deployable invasive device includes a transducer with a plurality of elements linked by at least one shape memory material configured to move the plurality of elements relative to one another between a first configuration and a second configuration in response to a stimulus. The shape memory material comprises at least one active region configured to facilitate transition between the first configuration and the second configuration. The deployable invasive device includes at least one integrated circuit configured to process signals from at least one of the plurality of elements and a plurality of conductive traces on or in the shape memory material and extending through the active region. The conductive traces are configured to conduct signals to the at least one integrated circuit, wherein the conductive traces are configured to conform as the shape memory material moves the elements between the first configuration and the second configuration.

Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.

Abstract: An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.

Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.

Abstract: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.

Abstract: An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.

Abstract: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.

Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.

Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: A substrate stack is suspended within a stack holder to position upper and lower stack surfaces coplanar with upper and lower holder surfaces. Laminating heat and pressure is simultaneously applied to the upper and lower surfaces to laminate a carrier interconnect film to top and bottom stack portions simultaneously. Subsequent wet chemical processing of both stack edges may also be simultaneous to effect savings in manufacturing costs.

Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.

Abstract: In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.

Abstract: A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached.