Patents by Inventor Kevin M. Hill

Kevin M. Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145885
    Abstract: Cell assemblies and methods for assembling cell assemblies include installing a plurality of cells within a cell housing and electrically connecting each cell to each other cell through at least one wire bond, wherein each wire bond is selected to conduct current from a respective cell during normal operation and to sever such electrical connection through the wire bond when a predetermined current exceeds a threshold value for a predetermined period of time.
    Type: Application
    Filed: February 15, 2022
    Publication date: May 2, 2024
    Inventors: Kyle James HILL, Kevin Andrew NOLTE, Juan M. MARTINEZ VALENCIA, Jason KRENTZ, John Kenneth GEORGE
  • Patent number: 6963991
    Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: November 8, 2005
    Assignee: Intel Corporation
    Inventors: Kevin M. Hill, Chris D. Matthews, Amir A. Bashir, Kevin E. Arendt, Andrew M. Volk
  • Publication number: 20030226052
    Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 4, 2003
    Inventors: Kevin M. Hill, Chris D. Matthews, Amir A. Bashir, Kevin E. Arendt, Andrew M. Volk