Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Abstract: A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

Abstract: A field effect transistor device has a semiconductor substrate having a predetermined impurity concentration of a first conductivity type. Inpurity layers of a second conductivity type are formed spaced apart at the main surface of the semiconductor substrate. The impurity layers make up source/drain regions. A region between the impurity layers defines a channel region. A notch-shaped conductive layer is formed on the channel region. The notch-shaped conductive layer has an upper layer section longer than a lower layer section. The upper and lower layer sections are formed of at least two different materials, one being silicon-germanium layer with varying germanium content. The material of the lower layer section can be etched at a greater rate than the material of the upper layer section during a common etching process.

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Abstract: A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.

Abstract: A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.

Abstract: A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.

Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan