Abstract: A fill head apparatus includes at least one chamber for holding a fluid. The chamber has an outlet for expelling the fluid. A vacuum device has an inlet for a suction device adjacent to the fluid outlet. A plurality of flexible and resilient sealing devices contact a top surface of a workpiece. The sealing devices are positioned on opposing sides of the chamber outlet and on opposing sides of the vacuum device inlet, such that the sealing devices create at least a partial seal around a cavity defined by the workpiece and the cavity is beneath both the chamber outlet and the vacuum outlet.

Abstract: A fill head apparatus includes at least one chamber for holding a fluid. The chamber has an outlet for expelling the fluid. A vacuum device has an inlet for a suction device adjacent to the fluid outlet. A plurality of flexible and resilient sealing devices contact a top surface of a workpiece. The sealing devices are positioned on opposing sides of the chamber outlet and on opposing sides of the vacuum device inlet, such that the sealing devices create at least a partial seal around a cavity defined by the workpiece and the cavity is beneath both the chamber outlet and the vacuum outlet.

Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.

Abstract: A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.

Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or holes in the outer few layers with the outer most layer not being filled with a conductor, such that a partially filled via or hole is produced. This effectively produces a smaller surface conductor feature, on which the semiconductor chip is temporarily attached, electrically tested, and subsequently removed using various methods, at forces much lower than normal chip removal processes require.

Abstract: A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates.

Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. Methods for forming tunnels through lamination and etching are employed. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates. Alternating semiconducting materials are introduced within the varying thermal conductivity layers by punching vias within greensheets of predetermined thermal conductivity and filling with n-type and p-type paste.

Abstract: A compliant, high-density land grid array connector and the process of making such a connector. The process includes the steps of: (a) forming holes in a supporting substrate; (b) forming threaded sidewalls by tapping the holes; (c) plating the threaded sidewalls to form bellows-like structures; and (d) etching a surface of the supporting substrate after the plating to leave portions of the bellows-like structures protruding past a surface of the substrate. The resulting connector includes a substrate having bellows-like contacts extending from one or both sides for resiliently engaging pads such as those of an LGA module. As an alternative, the holes may be formed as blind holes. Ends of the bellows-like contacts may be roughened. The connector may also be formed by casting the substrate in a mold box having screw-like mandrels followed by steps of mandrel removal, hole plating and surface etching.

Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. Methods are employed for forming tunnels through lamination and etching. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates. Alternating semiconducting materials are introduced within the varying thermal conductivity layers by punching vias within greensheets of predetermined thermal conductivity and filling with n-type and p-type paste.

Abstract: A surface mounted electronic interconnect device. The device includes a coaxial electrical pad comprising a plurality of conductive surfaces on a substrate corresponding to the conductor arrangement of a coaxial connector; and, a coaxial connector comprising a dielectric material having a center opening and isolated electrically conductive interior and exterior surfaces that are planar with the ends of the connector. The dielectric separates the inner conductive surface from the outer conductive surface and is tubularly shaped having an inner wall for the electrically conductive interior surface. The coaxial connector inner and outer conductors may alternatively be comprised of microsprings. The coaxial connector has first and second ends, the first end for attachment to an electronic package and the second end for pluggable attachment to a PC board.

Abstract: Disclosed is an SOFC having a catalytic anode including a porous, ceramic anode including a catalyst, wherein the catalyst is selected from the group consisting of platinum, rhodium, ruthenium and mixtures thereof; a dense, solid electrolyte adjacent to the porous, ceramic anode; a porous, ceramic cathode adjacent to the dense, solid electrolyte; and a dense, ceramic interconnect adjacent to the porous, ceramic cathode, wherein the dense, ceramic interconnect has nonintersecting passages for the flow of a fuel and an oxidant. Also disclosed is a method to make the SOFC having a catalytic anode.

Abstract: Disclosed is a method of making a solid oxide fuel cell with controlled porosity by varying the size of the ceramic particles, the type of organics, the sintering cycle and the amount of catalyst.

Abstract: One aspect of the invention relates to an interconnect for an SOFC wherein the interconnect is made from a cermet including partially stabilized tetragonal zirconia and a superalloy that is resistant to oxidizing and reducing conditions. Another aspect of the invention relates to an SOFC having vias for carrying fuel and an oxidant and at least one patterned feature in the anode, electrolyte, cathode and/or interconnect for laterally distributing the fuel or oxidant.

Abstract: Multiple vias are produced coaxially or in axis parallel alignment in a first or primary through-hole in a printed circuit board, chip carrier or like electrical device by producing a primary metallized through hole or via which is then filled or coated with a dielectric material which is also placed on both surfaces of the device at the ends of the via. The dielectric material inside the via can then be provided with at least one coaxial through-hole or multiple axis parallel through holes which can be metallized to form conductive paths between the surfaces of the device. Portions of the dielectric surface layer can be removed to expose contacts to the inner metallized via. Successive coaxial vias can be made in any number by the method of the invention. In addition electrical signal paths can be isolated within voltage or ground co-axial conductors.