Abstract: An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

Abstract: An improved CMOS driver circuit for driving a fast, single-ended, wired-or bus architecture. The driver circuit provides a user-selectable active deassertion assist feature which assists a passive terminator circuit in quickly pulling-up a data or control bus line. The resulting driver circuit provides greater noise immunity to negative voltage transients that result from impedance mismatches caused by poor cable design configurations.