Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.

Abstract: System and method for limiting power consumption in add-in expansion cards. A preferred embodiment comprises retrieving power consumption information for the add-in card, receiving power limit information for the expansion bus, determining if the add-in card is over power, and reducing the add-in card's power consumption if the add-in card is over power. The reducing can involve disabling the add-in card completely or disabling certain functions of the add-in card based upon an amount that the add-in card is over power.

Abstract: A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this address along with the data from the PCI device in the PCI transaction queues. When the data is transmitted along the PCI Express fabric, or when it is processed within the PCI Express to PCI bridge, the address assigned to the respective grant line becomes the PCI Express traffic class for that data. This enables the commands from one device to be processed irrespective of commands from other PCI devices on the PCI bus.

Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.

Abstract: A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station without additional connectors on the portable computer and the docking station.

Abstract: A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this address along with the data from the PCI device in the PCI transaction queues. When the data is transmitted along the PCI Express fabric, or when it is processed within the PCI Express to PCI bridge, the address assigned to the respective grant line becomes the PCI Express traffic class for that data. This enables the commands from one device to be processed irrespective of commands from other PCI devices on the PCI bus.

Abstract: A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the bridge. Data from the PCI device is assigned via a port arbitration table to sufficient bandwidth so that the data from the PCI device can be transferred upstream isochronously. The bridge also handles downstream isochronous data transfer.

Abstract: The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The system provides structures and methods that interface a PCI environment (106) with a PCI-Express environment (104). The present invention provides a PCI to PCI-Express bridge device (110) that is communicatively linked (112, 114) to the PCI and PCI-Express environments. The bridge device comprises a translation function (116) that is communicatively linked (120, 122) to the PCI and PCI-Express environments. A serialized interrupt is signaled from the PCI environment, and the translation function generates a message signaled interrupt within the PCI-Express environment based on that serialized interrupt.

Abstract: The present invention provides a system for conducting communications in a PCI-Express system (300). The PCI-Express system is interfaced with a system utilizing another protocol—particularly PCI. The present invention provides a segregation structure (302) within the PCI-Express system. A data transaction, from the PCI system to the PCI-Express system, is initiated. Data transmission is routed through the segregation structure, which operates such that corrupted data within the data transmission is identified and separated from uncorrupted data within the data transmission. The present invention transmits the corrupted data separately from the uncorrupted data.

Abstract: A media card core is separated into a media encryption function decryption circuit which remains in hardware on the peripheral side of a PCI bus. The command function generator for the media card is separated and performed in the CPU. All information flow across the PCI bus is encrypted with the media encryption function or a second encryption function such as DES so as to impede access to the command structure or the data encrypted on the media card by unauthorized persons.