Patents by Inventor Kevin McCall

Kevin McCall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12247272
    Abstract: Disclosed herein are embodiments of an Al—Ce—Cu alloy for use in additive manufacturing. The disclosed alloy embodiments provide fabricated objects, such as bulk components, comprising a heterogeneous microstructure and having good mechanical properties even when exposed to conditions used during the additive manufacturing process. Methods for making and using alloy embodiments also are disclosed herein.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: March 11, 2025
    Assignees: UT-Battelle, LLC, Lawrence Livermore National Security, LLC, Iowa State University Research Foundation, Inc., University of Tennessee Research Foundation
    Inventors: Sumit Bahl, Ryan R. Dehoff, Hunter B. Henderson, Scott McCall, Ryan Ott, Alexander J. Plotkowski, Orlando Rios, Amit Shyam, Zachary C. Sims, Kevin D. Sisco, David Weiss, Ying Yang
  • Patent number: 5793239
    Abstract: A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: August 11, 1998
    Assignee: Analog Devices, Inc.
    Inventors: Janos Kovacs, Kevin McCall
  • Patent number: 5646968
    Abstract: A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: July 8, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Janos Kovacs, Ronald Kroesen, Kevin McCall