Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: An aspect includes multi-channel nonvolatile memory management. A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: An integrated Circlet chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

Abstract: More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one..

Abstract: A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model.

Abstract: Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.