Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.

Abstract: A method, a system and a computer program product for influencing ranking of URLs in a search engine. In an example embodiment, a computer determines that a posting of a URL has occurred in a social networking environment, the computer tracks accesses of the URL subsequent to the posting of the URL. The computer further determines whether a number of accesses of the URL has increased subsequent to the posting of the URL and, responsive to determining that the number of accesses of the URL has increased subsequent to the posting of the URL, the computer determines whether the number of accesses of the URL has increased by at least a predefined threshold. Further, responsive to determining that the number of accesses of the URL has increased by at least the predefined threshold, the computer increases the ranking of the URL in a search engine.

Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.

Abstract: A method, a system and a computer program product for influencing ranking of URLs in a search engine. In an example embodiment, a computer determines that a posting of a URL has occurred in a social networking environment, the computer tracks accesses of the URL subsequent to the posting of the URL. The computer further determines whether a number of accesses of the URL has increased subsequent to the posting of the URL and, responsive to determining that the number of accesses of the URL has increased subsequent to the posting of the URL, the computer determines whether the number of accesses of the URL has increased by at least a predefined threshold. Further, responsive to determining that the number of accesses of the URL has increased by at least the predefined threshold, the computer increases the ranking of the URL in a search engine.

Abstract: An apparatus and system are disclosed for filtering third-party generated content in a social network. A receive module receives, from a requesting third-party user, a request to view third-party generated content that is generated by one or more third-party users of a social network. A group module determines one or more group permissions set by a user for one or more groups. The one or more group permissions define access to the third-party generated content. A filter module filters the third-party generated content according to the one or more group permissions such that the third-party generated content is filtered prior to presentation of the third-party generated content to the requesting third-party user in response to the request.

Abstract: An apparatus, system, and method are disclosed for filtering third-party generated content in a social network. The method may involve receiving a request to view third-party generated content in a social network. The method may involve determining the group permissions that are set by the user for one or more groups. The user may define group membership. The group permissions define the access privileges to the third-party generated content. The method may also involve filtering the third-party generated content according to the group permissions such that the third-party generated content is filtered prior to its presentation to the requesting third-party user. As a result, certain third-party generated content may be hidden from certain third-party users. In certain embodiments, the user can set individual permissions governing access to the third-party generated content.

Abstract: An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the system and method disclosed herein, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.

Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

Abstract: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the system and method disclosed herein, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.